NA62 front end Layout in DM option

Jan Kaplon/Pierre Jarron

Architecture

Preamp; buffered cascode (NMOS input transistor), resistive feedback (200k)

Gain;70mV/fC (25mV/fC at preamp output)

Preamplifier AC coupled to shaper and discriminator stages

Consumption; 190uA/pixel (70uA in analog section, 40uA digital part of comparator, 80uA line driver )

Feedback ;Cf=15 fFRf= 200kInput transistor; NMOS 9.6/0.3um

2 DFF added per cell for calibration input and masking of the output

DM 3-2 metallization option

DM 3-2 metallization option

DM 3-2-3 resistance/sq min width/distance M1,M2,M3 ~60mOhm/sq 0.2um/0.2um MQ,MG ~35mOhm/sq 0.4um/0.4um LY (Al, MIM) ~89mOhm/sq 0.6um/0.8um E1 ~6mOhm/sq 1.5um/2um MA (Al, pad) ~7mOhm/sq 4um/5um

Pixel layout

Input pad with MA; 26um metal/20um opening (identical to MEDIPIX)

Power distributed with MA (35um bars for analog, 5um for digital), biases distributed with E1

Advantages of DM option

Low resistances for column supply bars; 3 mOhm for analog supplies (3.6mA consumption), 20 mOhm for digital (5.4mA consumption) Small and simple layout of input pad (MA layer 4um thick Al) Availability of MIM capacitors (coupling capacitor smaller by 30% comparing to vertical capacitors)

Noise

5ns peaking time CR-RC1

Input transistor bias; 40uA, Feedback resistor 200kΩDetector leakage; 20nA

Open loop gain simulation

Gain Bandwidth Product 900MHz (simulation for compensated cascode)

Input impedance simulation

Input impedance 1 – 2kΩ

Phase margin simulation

Phase margin for Cinput 250fF ; 90⁰

Phase margin simulation

Phase margin for Cinput 500fF ; 87⁰

Transient simulation

Peaking time; 4.5ns at preamp, 5.5ns at discriminator input

1st differential stage output

Preamp output

Discriminator output

Transient simulation

Good linearity and no degradation of peaking time up to 4fC (1,1.2, 3, & 4fC signals)

Differential signal as seen by comparator input

threshold

Transient simulation

Double pulse resolution; 2 signals 3fC in 20ns distance at 0.7fC threshold

1st differential stage output

Preamp output

Discriminator output

Transient simulation

Walk; 1.5ns for 1.2 and 4fC (0.7fC threshold)

Walk; 2ns for 1 and 4fC (0.7fC threshold)

Pulse width; 8 to 14ns (1 to 4fC)

Discriminator output

Power Supply Rejection Ratio (discriminator differential input)

Low and medium frequencies; 48dB, degrading after 1MHz

Worst case; 5dB at 100MHz

PSRR

200ps edge, 5mV on analogue and 50mV on digital

Discriminator input, (differential) 1fC signal (65mV)

2.5mV pick-up from analog supply

1st differential stage output(discriminator input)

no pick-up from digital supply

Mismatch (without TRIM DACs)

3fC signal, mismatch 6mV RMS (0.1fC RMS) minimum threshold without trimming 0.7fC

Assuming 5-bit TRIM DAC with 50mV range the mismatch can be minimized down to 1.5mV pk-pk (0.25mV RMS)

Discriminator input (differential,) 3fC signal

Mismatch (without TRIM DACs)

3fC signal, mismatch 6mV RMS, 300ps RMS (1.7ns pk-pk)

Discriminator output

Noise & Jitter (transient noise simulation)

3fC signal, noise ~2mV RMS, ~200e- RMS

Discriminator input (differential,) 3fC signal with noise

Noise & Jitter (transient noise simulation)

3fC signal, noise ~200e- RMS jitter 30ps RMS (160ps pk-pk)

Discriminator output (with output jitter)