panzer division 2.0 16-bit central processing unit
TRANSCRIPT
Panzer Division 2.0Panzer Division 2.0
16-bit Central Processing Unit16-bit Central Processing Unit
Team MembersTeam Members
Eric BowdenEric Bowden
Philip ChristensenPhilip Christensen
Waylon GrangeWaylon Grange
Adam ThompsonAdam Thompson
LogisticsLogistics
Division of laborDivision of labor
TimelineTimeline
Division of laborDivision of labor
CPU controlCPU controlBlock RamBlock RamFlash InterfacingFlash InterfacingAssemblerAssemblerIO Devices:IO Devices:
--SoundSound--DisplayDisplay--Game pad/controllerGame pad/controller
Previous DivisionPrevious Division
ALUALUCode Writer = EricCode Writer = Eric
Tester = WaylonTester = Waylon
Hardware = PhilHardware = Phil
Report = AdamReport = Adam
RegisterRegisterCode Writer = WaylonCode Writer = Waylon
Tester = AdamTester = Adam
Hardware = PhilHardware = Phil
Report = EricReport = Eric
Preliminary Assignments Preliminary Assignments
CPU controlCPU control = Phil= PhilBlock Ram Block Ram = Waylon= WaylonFlash Interfacing Flash Interfacing = Phil= PhilAssembler Assembler = Phil & Waylon= Phil & Waylon– CompilerCompiler = Adam & Phil= Adam & Phil
IO Devices: IO Devices: = Eric & Adam= Eric & Adam--SoundSound = Eric & Adam= Eric & Adam--DisplayDisplay = Eric & = Eric &
WaylonWaylon--Game pad/controllerGame pad/controller = Eric & Adam= Eric & Adam
Tentative Timeline Tentative Timeline
CPU controlCPU control = Oct. 18= Oct. 18Block Ram Block Ram = Oct. 14= Oct. 14Flash Interfacing Flash Interfacing = Oct. 10= Oct. 10AssemblerAssembler = Oct. 10= Oct. 10IO Devices: IO Devices:
--SoundSound (time permitting) (time permitting) --DisplayDisplay = Oct. 24= Oct. 24--Game pad/controllerGame pad/controller = Oct. 28= Oct. 28
ALU
Registers
Data_A [16]
Alu_opcode [8]
Immediate
extend
Data_B_reg[16]
B_reg_write
Psr_alu [16]
ALU_result [16]
writeback
Immed_value[16]
Immed_instruction[8]
Sign_extend
Re
set_
reg
Re
g_w
rite
[4]
A_
ou
t[4]
B_
ou
t[4]
Rsrc_alu[16]
PSR
Psr_out[16]
1 .
0 .
Write_PSR
Instruction memory
PCDecode(control)
Inst
ruct
ion
[16
]
+
1
Branch logic
Branch_code[4]
Branch_type[2]
+
Data Memory
StatisticsStatistics
SlicesSlices Slice Flip Slice Flip FlopsFlops
4-Input 4-Input LUTsLUTs
Max Max DelayDelay
ALUALU 9090 00 159159 31.10 ns31.10 ns
Register Register FileFile 238238 256256 416416 21.75 ns21.75 ns
ControlControl 88 22 1515 15.54 ns15.54 ns
ArchitectureArchitecture
MemoryMemory– Separate memory for Instructions & DataSeparate memory for Instructions & Data– Data Memory currently in block ram Data Memory currently in block ram
768x16 + 256x16 = 1024x16768x16 + 256x16 = 1024x16Block ram is fastBlock ram is fast
– Instruction memory currently in flashInstruction memory currently in flash64K x 1664K x 16Finite state machine reads from flashFinite state machine reads from flashSlowest component limits clock to 10Mhz (20Mhz if Slowest component limits clock to 10Mhz (20Mhz if we are tricky)we are tricky)
ArchitectureArchitecture
PipeliningPipelining– Not part of baseline, but we want to do itNot part of baseline, but we want to do it– No stalls waiting for memory because of No stalls waiting for memory because of
separationseparation– Followed MIPS (pipeline work has already Followed MIPS (pipeline work has already
been done)been done)– Clock limited to 10MhzClock limited to 10Mhz– Data forwarding unit avoids data hazardsData forwarding unit avoids data hazards– Software avoids jump/branch hazardsSoftware avoids jump/branch hazards
ALU
Registers
Data_A [16]
Alu_opcode [8]
Immediate
extend
Data_B_reg[16]
B_reg_write
Psr_alu [16]
ALU_result [16]
writeback
Immed_value[16]
Immed_instruction[8]
Sign_extend
Re
set_
reg
Re
g_w
rite
[4]
A_
ou
t[4]
B_
ou
t[4]
Rsrc_alu[16]
PSR
Psr_out[16]
1 .
0 .
Write_PSR
Instruction memory
PCDecode(control)
Inst
ruct
ion
[16
]
+
1
Branch logic
Branch_code[4]
Branch_type[2]
+
Data Memory
Input Output InterfacesInput Output Interfaces
Major InterfacesMajor Interfaces– AudioAudio– VGA MonitorVGA Monitor– SNES ControllerSNES Controller
Input Output InterfacesInput Output Interfaces
Major InterfacesMajor Interfaces– AudioAudio– VGA MonitorVGA Monitor– SNES ControllerSNES Controller
Two OptionsTwo Options– Audio IC Chip - ISD Audio IC Chip - ISD
1600 ChipCorder1600 ChipCorderTwenty seconds of Twenty seconds of addressable audioaddressable audio
– Off-board Off-board Preprogrammed Music Preprogrammed Music GeneratorGenerator
CS3700 Final ProjectCS3700 Final Project
Input Output InterfacesInput Output Interfaces
Major InterfacesMajor Interfaces– AudioAudio– VGA MonitorVGA Monitor– SNES ControllerSNES Controller
ISD 1600 ChipCorderISD 1600 ChipCorder
Input Output InterfacesInput Output Interfaces
Major InterfacesMajor Interfaces– AudioAudio– VGA MonitorVGA Monitor– SNES ControllerSNES Controller
Music GeneratorMusic Generator
Input Output InterfacesInput Output Interfaces
Major InterfacesMajor Interfaces– AudioAudio– VGA MonitorVGA Monitor– SNES ControllerSNES Controller
Video SpecificationVideo Specification– 64 pixels by 32 lines64 pixels by 32 lines
– 2-bit pixels (Four 2-bit pixels (Four colors)colors)
Memory RequirementsMemory Requirements– Chosen resolution fits Chosen resolution fits
in block RAM modulein block RAM module64x32x2 = 4096 bits 64x32x2 = 4096 bits
= 4 = 4 KBKB
Input Output InterfacesInput Output Interfaces
Major InterfacesMajor Interfaces– AudioAudio– VGA MonitorVGA Monitor– SNES ControllerSNES Controller Pin Description Wire Color
1 +5v White
2 Data Clock Yellow
3 Data Latch Orange
4 Serial Data Red
5 N/C -
6 N/C -
7 Ground Brown
7-pin Human Interface Device7-pin Human Interface Device
Input Output InterfacesInput Output Interfaces
Major InterfacesMajor Interfaces– AudioAudio– VGA MonitorVGA Monitor– SNES ControllerSNES Controller
Controller uses a Controller uses a serial communication serial communication methodmethod
A FSM will eat the 16 A FSM will eat the 16 bits of control data 1 bits of control data 1 bit at a timebit at a time
Data stored in a free Data stored in a free floating registerfloating register
NibblesNibbles
PipeliningPipelining
In pipelined systems jump require “bubbles” to execute correctly
This can be implemented in assembly by inserting NOPs
ALU
Registers
Data_A [16]
Alu_opcode [8]
Immediate
extend
Data_B_reg[16]
B_reg_write
Psr_alu [16]
ALU_result [16]
writeback
Immed_value[16]
Immed_instruction[8]
Sign_extend
Re
set_
reg
Re
g_w
rite
[4]
A_o
ut[4
]
B_
out[4
]
Rsrc_alu[16]
PSR
Psr_out[16]
1 .
0 .
Write_PSR
Instruction memory
PCDecode(control)
Inst
ruct
ion[
16]
+
1
Branch logic
Branch_code[4]
Branch_type[2]
+
Data Memory
Code implemented jumpsCode implemented jumps
MOVI $tmp, 1
CMPI $regb, 0
BNE _ifgrow
STOR $rega, $tmp
//IF (grow == 0)
//Move 1 into *head
Evolution of NibblesEvolution of Nibbles
What’s nextWhat’s next
Make your own Game!Make your own Game!
TronTron
MillipedeMillipede
TetrisTetris
?!?!
TestingTesting
Best tests Best tests ShouldShould be in the writing. be in the writing.
->Write using “Test First” method->Write using “Test First” method
Second stage “Black Box” testing.Second stage “Black Box” testing.
Optional Third Stage “White Box” testing.Optional Third Stage “White Box” testing.
Questions?Questions?