presentazione standard di powerpoint - crit · 8gb emmc micro-b usb device connector usb-to-uart...
TRANSCRIPT
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AXIOM Boardsignal integrity, setup a cluster and power management
18th october 2017
Ing. Alessandro Pali Ing. Davide [email protected] [email protected]
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AXIOM Ecosystem
H2020 allowed SECO to invest in the Programmable hybrid
ARM/FPGA SoCs area bringing new solutions to the embedded market
through relationships with both industrial and academic partners
ACADEMIC PARTNERSINDUSTRIAL PARTNERS
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Clustering capabilities
OmpSs framework
Software
Open source OSHybrid SoC
Compatibility with Arduino
Cost-effective networing infrastructure
Hardware
ARM based
AXIOM BoardHardware and Software Stack Solution
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BOOTMEDIA
AXIOM LINK
Video outputs
Zynq Ultrascale+ ZU9EG MPSoC
Gigabit Ethernet
transceiver
2 x USB 3.0
Type-A connectors
JTAG connector
QSPI Flash
microSD
connector
DDR4 ECC
So-DIMM
RJ-45 Ethernet
connector
2 x USB 2.0 ULPI
Transceivers
mini-DP connector
Camera Connector
LVDS connector
Clock generator
1GB 32-bit
Soldered down
DDR4 memory
8GB eMMC
micro-B USB
Device connector
USB-to-UART
bridge
Arduino UNO
connectors
Trace port
connector
HSDP connector
USB Type-C
connectors #[0..3]
Cable orientation
detection logic
Processing
system
RGMII
ULPI #[0..1]
USB SS #[0..1]
eDP
DDR4
JTAG
QSPI
SDIO #0
SDIO #1
UART #0
Programmable
Logic
LVDS
DDR4
GPIO
TRACE
PORT
HSDP
GTH Transceivers
REFCLK
GTH
#[0..3]Power supply
-
Power monitors
Hardware Prototype
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Dedicated On-Board Hardware:
Power measurements on 8 supply
rails (70% of maximum total
estimated power)
Specific Development Tools Cross
Triggering Capabilities During Debug
and Trace:
Dedicated test points for analog
probe connections and ‘Breakpoint’
on given power consumption levels
I2C bus
Zynq
SoC
VCC
ON BOARD POWER MONITOR
ANALOG PROBE
SHUNT
RESISTOR
• APPLICATIONS CAN TRACK POWER CONSUMTPION AGAINST RUNNING TASKS
• USERS MAY TEST CODING STYLES AGAINST POWER CONSUMPTION
AXIOM id. 645496
http://www.axiom-project.eu/deliverable
Power Monitoring and Profiling
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SMART SURVEILLANCE
SMART HOME
SMART ENERGY
SMART HEALTH
SMART CARDO- IT-YOURSELF
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First Outcome for SECOIndustrial solution SM-B71
Wide scalability from cost effective
Dual-Core to high performance
Quad-Core ARM® Cortex®-A53
MPSoCs with GPU/VCU
Dedicated Real-Time ARM® Cortex®-
R5 processors
Extreme flexibility: up to 256k FPGA
logic cells
LVDS and DP video interfaces up to
4K resolution High-speed interfaces
SMARC Rel. 2.0 with the Xilinx® Zynq® Ultrascale+™ MPSoC
SM-B71
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EMC evaluation and Signal Integrity
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EMC evaluation & Signal IntegrityProduct Research and Development
What SECO EMC division for measurements
and certifications does:
▪ Design of HS digital lines
▪ Post layout symulations
▪ Signal integrity measurements
▪ Pre-conformity EMI/EMS measurements
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Pre Layout Vias tecnology
Pre-layoutTo verify the improvement
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At the pre-layout stage we can
define the budget we need to
garant a correct routing of the
board.
At the pre-layout stage we can
evaluate the surface roughness,
xtalk etc. effects yet.
Pre-layoutUSB 3.0
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At pre-layout stage we
can also define the
equalization’s parameters
we need to garant that
the involved bus does
work correctly.
Pre-layoutUSB 3.0
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VIA simulato con Momentum
It can be useful to define general
rules valid for all the data or
addresses of a DDR, helping the CAD
projectist to route a board that
already has predefined distances
and matchings.
To make the pre-layout stage closer
to a real situation, VIASes can be
extracted with ADS or EMPro.
Pre-Layout AnalysisSimulation Bus DDR4
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DDR before and after the optimization with ADS
ADS is a powerful optimization instrument
to improve our transmission line.
We used eye width and skew interchip
as optimization parameters to stay in the
standards managed by the processor
controller to have a fly-by topology.
Those parameters would change for a T
topology where the main problems are
reflections not the xtalk.
Pre-Layout OptimizationSimulation Bus DDR4
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PDN extracted with EM simulation
Impedance saw from the CPU with an AC
simulation
Decoupling capacitors and EMI suppressor
include real elements: only with
symulations we can comprehend the real
impedance profile.
Power Integrity Analysis
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PCB EMI compliance analysisRFEM 3D EM Simulation in EMPro with EMI Emission Calculation
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ESD AnalysisFTDT 3D EM Simulation with EMPro
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Antenna matching network
designed extracting S
parameters with EMPro and
optimization of the fine tuning
elements with ADS optimization
WiFi antenna on PCBAnalisi FEM with EMPro
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Keysight ADS 2017Signal and Power Integrity Solutions
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Keysight ADS 2017Signal and Power Integrity Solutions
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AXIOM BoardImported in ADS
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AXIOM BoardImported in ADS
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AXIOM BoardImported in ADS
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S-Parameter MeasurementWith Keysight ENA
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S-ParametersSimulated vs Measured
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Eye Diagram Test BenchIn ADS
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Eye Diagram MeasurementWith Keysight V-Series Scope
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Measured Simulated
Eye DiagramSimulated vs Measured
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Control of whichbusses need a
prelayout
High speed digital design
USB3.0, DDR,
SATA, DDI ecc.
EMC and SI simulations
Mass production
Pre-SeriesPost Layout Verification
Electric Scheme
3D Solver EMCsimulations
Far field ESDsimulations
Specifications
PCB Design
Proto
Project time
Production Costs
Number of Revisions
Design Flow: Now
Definition of Layout rules, optimized stack up
for HSD
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Thank You
Ing. Alessandro Pali Ing. Davide [email protected] [email protected]
www.seco.com
SECO s.r.l.
Via Calamandrei, 91
52100 Arezzo - ITALY
Ph. +39 0575 26 979
Fax +39 0575 350 210