rf-soi for rffe solution: eda...

RF-SOI for RFFE Solution: EDA Perspective

Feng Ling, Ph.D.

Founder and CEO

2018 Japan SOI Workshop

Xpeedic Confidential Page 2

Outline

• Design challenges for RFFE from EDA perspective

• Xpeedic’s solution for RF-SOI• EDA tools enabling both silicon and module

• IPD enabling integration and miniaturization for RFFE

• Summary


Design Challenges

• RFFE design challenges• More complexity

• More components, e.g. MIMO and CA filter

• More performance demand, high isolation, low IL

• Smaller size

• Lower cost

• EDA for RFFE design need support• Multiple technology

• High frequency, mmWave

• Filter, antenna design

• Advanced packaging, FOWLP, Interposer, 3DIC

• More EM content• EM-circuit simulation• Integrated IC-package design flow• Antenna, filter design integrated


Xpeedic Solution

•Electromagnetics-aware IC-Package-Board solution

EDA

Example text

SiP

• System-in-Package (SiP)• RF module with IPD

•First-pass IPD design flow•IPD library available•Turn-key customized IPD design

IPD

IPD

SiPEDAStacked Die

2.5D IC(Si Interposer)

XPEEDIC EDA FOR RF-SOI


EDA Solution from IC to System

ICPKG

System

❑ Passive modeling and extraction for advanced node.

❑ Signal and power integrity analysis for advanced packaging

❑ System level channel analysis

❑ Accurate modeling of via, trace, and cable.

Foundation: 3D Electromagnetic solver technologies


Virtuoso-Integrated IC Design Flow

System Design

Schematic Design

Circuit Simulation

Layout

Verification

Tapeout

IRISPassive extraction

iModelerPassive modeling and

synthesis

MetisIC-package co-simulation

Include Package

HFSS

Passive verification

IRIS-HFSS


• IRIS solver technology• Fast: Accelerated MoM technology

• Accurate: 3D conductor and via model, skin effect and proximity effect

• Advanced process support• Width/spacing dependence

• rho table, bias table

• Seamlessly integration in Cadence Virtuoso

IRIS: Virtuoso-integrated EM Simulation Tool

350nm 130nm 90nm 28nm 14nm


IRIS-HFSS Flow

HFSS 3D Layout Q3D

IRIS-HFSS

Thin layer treatment

Rho-table support

Bias-table support

Via defeaturing support

Auto HFSS/Q3D generation

De-embed


iModeler: Automated Fast PDK Model Generation

Foundry PCells

Templates for• Inductor• MiM Cap• MoM Cap• Transformer

Process Technology

Shielding/Dummy

DRC Rule Deck LVS Rule Deck

Schematic/Layout/Symbols

Synthesis Databse

Spectre/HSPICE Scalable Model

ANN Engine

Optimize MoM Solver

PDKTemplate

Core

Process

* *M


Metis 1: IC-Package Co-design Flow

• Example: IPD design in RFFE module

IncludePackage

LPF mounted on package substrateLow Pass Filter (LPF)

Spec(dB)

Freq (MHz)Spec value

NO PKGWith PKGMin Typ Max

IL 869-960 0.7 Pass Fail

RL 869-960 18 Pass Fail

RJ@2f 1738-1920 20 Pass Fail

RJ@3f 2607~2880 15 Pass Pass

Earlier package consideration in the flow is a must.


Metis 2: Silicon Interposer with TSV• 2.5D interposer with TSV enables heterogeneous

integration and delivers “More-than-Moore”

Silicon partition with interposerMarket: FPGA

Logic+memory on interposerMarket: CPU, GPU, network processor


• A complete model with layout and bumps

uBump

C4 Bump

Metis 2: Silicon Interposer with TSV (cont’d)

SI/PI Analysis

• A complete SI/PI analysis flow for silicon interposer with TSV and 3D IC.

Time (hour)

Metis 56 min

HFSS 7hr 50min

Return Loss Insertion Loss

XPEEDIC IPD ENABLE INTEGRATION FOR RF-SOI


What is IPD

• Integrated Passive Device• Thin film process

• High metal conductivity, high substrate resistivity

• Thin film resistor, MIM capacitor, Through substrate via, magnetic material…

• IPD advantages• Small size, low profile, friendly integration, great consistency, low cost

• Size and cost reduction for hand-held, wearable applications


IPD applications


Xpeedic IPD

IPD Suite

SiP Suite

IPD Foundries

Dedicated EDA Tools

High Resistivity Silicon

Glass

Through Glass Via


IPD Coupler XS0808C2G12FM12

0.8×0.8×0.2 mm3

LTCCcounterpart


IPD Balun XS0505B2G45WA20

LTCCcounterpart

0.5×0.5×0.35 mm3


IPD Diplexer XS0808D2G50WA03 XS1608D960MWA04

0.8×0.8×0.35 mm3

LTCCcounterpart

1.6×0.8×0.35 mm3

LTCCcounterpart


Summary

• RFFE design challenges requires EDA solution to support more complexity and integration;

• Xpeedic’s EDA solution has been certified in multiple RF-SOI technologies, which enables IC designers to design with confidence and thus achieve fast time-to-market;

• Xpeedic’s silicon-proven IP on IPD provides viable solution for RF front end integration.

rf-soi for rffe solution: eda...

Documents