sequential machine design - sharif
TRANSCRIPT
Sequential Machine Design and Implementation
Somayyeh KoohiDepartment of Computer Engineering
Sharif University of TechnologyAdapted with modifications from lecture notes prepared by author
Modern VLSI Design: Chap5 2 of 25Sharif University of Technology
Topics
n Retimingn Time borrowingn Sequential machine design
Modern VLSI Design: Chap5 3 of 25Sharif University of Technology
Clock period
n For each phase, phase period must be longer than sum of:vCombinational delayvLatch propagation delay
n Phase period depends on longest path
Modern VLSI Design: Chap5 4 of 25Sharif University of Technology
Unbalanced delays
§ Logic with unbalanced delays leads to inefficient use of logic:§ Lower clock frequency
long clock periodshort clock period
Modern VLSI Design: Chap5 5 of 25Sharif University of Technology
Retiming
§ Retiming moves memory elements through combinational logic:§ Changes circuit’s timing § Keep the functionality
Modern VLSI Design: Chap5 6 of 25Sharif University of Technology
Retiming properties
n Retiming changes encoding of values in registersv But proper values can be reconstructed with combinational
logicn Retiming may increase number of registers requiredn Retiming must preserve number of latches around a
cyclevMay not be possible with reconvergent fanout
Modern VLSI Design: Chap5 7 of 25Sharif University of Technology
Topics
n Retimingn Time borrowingn Sequential machine design
Modern VLSI Design: Chap5 8 of 25Sharif University of Technology
Advanced performance analysis
n Latch-based systems always have some idle logicvWaiting for the next latch to become active
n Can increase performance by blurring phase boundaries (time borrowing)vResults in cycle time closer to average of phasesvHigher frequency
Modern VLSI Design: Chap5 9 of 25Sharif University of Technology
Example with unbalanced phases
§ One phase is much longer than the other:
Modern VLSI Design: Chap5 10 of 25Sharif University of Technology
Spreading out a phase
n Compute only part of long paths in one phase (Ф1):
n Use other phase (Ф2) for end of long logic block and all of short logic block:
Modern VLSI Design: Chap5 11 of 25Sharif University of Technology
Example of time borrowing
Without time borrowing With time borrowing40
40
Φ1
Φ2
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Problems
n Feasible for latches, not FFsv Since FFs are edge triggered
n Hard to debugv Can’t stop the system
n Hard to initialize system state v Since some of that state is stored on wires in the
combinational logicn More sensitive to process variationsv Process variation changes combinational delaysv So, rarely used
Modern VLSI Design: Chap5 13 of 25Sharif University of Technology
Topics
n Retimingn Time borrowingn Sequential machine design
Modern VLSI Design: Chap5 14 of 25Sharif University of Technology
Sequential machine design
n Two ways to specify sequential machine:vStructure: interconnection of logic gates and
memory elementsvFunction: Boolean description of next-state and
output functionsn Best way depends on type of machine being
described
Modern VLSI Design: Chap5 15 of 25Sharif University of Technology
Counter
n Easy to specify as one-bit countern Harder to specify n-bit counter behaviorvCan specify n-bit counter as structure made of 1-
bit counters
Modern VLSI Design: Chap5 16 of 25Sharif University of Technology
One-bit counter
Truth table:count Cin next Cout
0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
next = count ⊕ CinCout = count & Cin
⇒
Modern VLSI Design: Chap5 17 of 25Sharif University of Technology
One-bit counter (implementation and operation)
n All operations are performed as sφ2
n XOR computes next value of this bit of countern NAND/inverter compute carry-out
Modern VLSI Design: Chap5 18 of 25Sharif University of Technology
One-bit counter stick diagramCout
VDD
VSSl1(latch) n(NAND) i(INV) x(XOR) l2(latch)
Cinφ1 φ1’ φ2 φ2’
Modern VLSI Design: Chap5 19 of 25Sharif University of Technology
n-bit counter structure
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State transition graphs/tables
n Basic functional description of FSMn Symbolic truth table for next-state, output
functions:vNo structure of logicvNo encoding of states
n State transition graph and table are functionally equivalentvTransition graph ó Transition table
Modern VLSI Design: Chap5 21 of 25Sharif University of Technology
01 string recognizer
Behavior of machine which recognizes “01” in continuous stream of bits:
time 0 1 2 3 4 5input 0 0 1 1 0 1state bit1 bit2 bit2 bit1 bit1 bit2next bit2 bit2 bit1 bit1 bit2 bit1output 0 0 1 0 0 1
n Waits for 0 to appear in state bit1n Goes into separate state bit2 when 0 appearsn If 1 appears immediately after 0, can’t have a 01 on next cycle
v So, can go back to wait for 0 in state bit1
Modern VLSI Design: Chap5 22 of 25Sharif University of Technology
State transition table and graph§ Symbolic state transition table:input present next output0 bit1 bit2 01 bit1 bit1 00 bit2 bit2 01 bit2 bit1 1
§ State transition graph (equivalent to state transition table):
v Mealy FSM
Modern VLSI Design: Chap5 23 of 25Sharif University of Technology
State assignment
n State assignment: must find binary encoding for symbolic states
n Choice of state assignment directly affects both the next-state and output logic:v Areav Delayv Power
Ø Efficient encoding reduces number of bit transition between adjacent states
n May also encode some machine inputs/outputs
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01 recognizer encoding
Choose bit1= 0, bit2 = 1:input present next output 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 1
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Logic implementation
§ After encoding, truth table can be implemented in gates: