techinical vlsi

Lab-Manual (VLSI Technology and Design) www.gecdahod.ac.in

Laboratory Manual

PART – II

VLSI Technology and Design B. E. SEMESTER: VI

Electronics & Communication Engineering

GOVERNMENT ENGINEERING COLLEGE, DAHOD

(GUJARAT TECHNOLOGICAL UNIVERSITY)

Term Date: 21-1-2013 to 18-5-2013

Prepared by: Prof. S. B. Prajapati

http://www.gecdahod.ac.in/


INDEX

Sr. No.

Title of the experiment Date Sign Marks

1 Introduction to Back-end Design Tools - Microwind.

2

Draw a layout of Resistive Load Inverter & CMOS Inverter using CMOS 0.12um technology and simulate its transient characteristics.

3 Draw a layout of CMOS NAND Gate using CMOS 0.12um technology and simulate its transient characteristics.

4 Draw a layout of CMOS NOR Gate using CMOS 0.12um technology and simulate its transient characteristics.

5 Draw a layout of CMOS Half Adder Gate using CMOS 0.12um technology and simulate its transient characteristics.

6 Draw a layout of CMOS Full Adder Gate using CMOS 0.12um technology and simulate its transient characteristics.

7 Compare Transfer Characteristics of CMOS, Resistive Load and NMOS Load Inverter.

8 Draw a layout of CMOS XOR Gate using CMOS 0.12um technology and simulate its transient characteristics.

9 Simulate Substrate Bias ( Body ) effect in CMOS inverter.



Experiment - 1

Aim : Introduction to Back-end Design Tools - Microwind.

MICROWIND TOOL

MICROWIND3 is user friendly layout and simulation tool for sub-micron CMOS design. The MICROWIND3 allows the designer to simulate and design an integrated circuit at physical description level. The package

contains a library of common logic and analog ICs to design and simulate. MICROWIND3 includes all the

commands for a mask editor as well as verification tools never gathered before in a single module.

MICROWIND3 is truly a complete and cost-effective design solution for your CMOS design.

nanoLambda VirtuosoFab MEMsim PROthumb PROtutor

DSCH Schematic editor and simulator User-friendly environment for rapid design of logic circuits.

Handles both conventional pattern-based logic simulation and intuitive on-screen mouse-

driven simulation. Supports hierarchical logic design.

Built-in extractor which generates a SPICE netlist from the schematic diagram (Compatible with

PSPICE™ and WinSpice™).

Current and power consumption analysis.

Generates a VERILOG description of the schematic for layout editor.

Immediate access to symbol properties (Delay, fanout). Sub-micron, deep-submicron, nanoscale technology support.

Supported by huge symbol library.



NanoLambda Precision CMOS Layout tool upto 35 nanometers. Sub-micron, deep-submicron, nanoscale technology support.

Unsurpassed illustration capabilities. Design-error-free cell library (Contacts, vias, MOS devices, etc..)

Advanced macro generator: capa, self, matrix, ROM, pads, path, etc..)

Incredible translator from logic expression into compact design-error free layout.

Powerful automatic compiler from VERILOG circuit into layout.

On-line design rule checker: width, spacing, overlap, extension rule verification.

Built-in extractor which generates a SPICE netlist from layout. Extraction of all MOS width and length.

Parasitic capacitance, crosstalk and resistance extracted for all electrical nodes.

Import/Export CIF layout from 3rd party layout tools.

Up to 100,000 elementary boxes.

Lock & unlock layers to protect some part of the design from any changes. Enhanced editing commands and layout control.

Support upto 8 metal layers for DSM technologies.

Global delay evaluation of circuit.

Global cross talk analyzer. Inversion of diffusions boxes.

Easy label listing.

Enhanced mathematical signal description.

Zoom in navigator.

Support till 22 nanometer technology.

Enhanced memory utilization for faster simulation. Silicon atom viewer.

Technology library available Minimum feature size Cmos12.rul 1.2mm

Cmos08.rul 0.7mm

Cmos06.rul 0.5mm Cmos035.rul 0.4mm

Cmos025.rul 0.25mm

Cmos018.rul 0.2mm

Cmos012.rul 0.12mm

Cmos90n.rul 0.1mm Cmos70n.rul 0.07mm

Cmos50n.rul 0.05mm



Experiment - 2

Aim : Draw a layout of Resistive Load Inverter & CMOS Inverter using CMOS 0.12um technology and simulate its transient characteristics.

(CMOS 0.12um TECHNOLOGY using Microwind3)

Simulation Waveforms



CMOS Inverter





Experiment - 3

Aim : Draw a layout of CMOS NAND Gate using CMOS 0.12um technology and simulate its transient characteristics. (CMOS 0.12um TECHNOLOGY using Microwind3)




Experiment - 4

Aim : Draw a layout of CMOS NOR Gate using CMOS 0.12um technology

and simulate its transient characteristics. (CMOS 0.12um TECHNOLOGY using Microwind3)




Experiment - 5

Aim : Draw a layout of CMOS Half Adder Gate using CMOS 0.12um technology and simulate its transient characteristics. (CMOS 0.12um TECHNOLOGY using Microwind3)




Experiment - 6

Aim : Draw a layout of CMOS Full Adder Gate using CMOS 0.12um technology and simulate its transient characteristics.





Experiment - 7

Aim : Compare Transfer Characteristics of CMOS, Resistive Load and NMOS Load Inverter. (CMOS 0.12um TECHNOLOGY using Microwind3)



Experiment - 8

Aim : Draw a layout of CMOS XOR Gate using CMOS 0.12um technology and simulate its transient characteristics. (CMOS 0.12um TECHNOLOGY using Microwind3)




Experiment - 9

Aim : Simulate Substrate Bias ( Body ) effect in CMOS inverter.




techinical vlsi

Documents

compare transfer characteristics

nanoscale technology support

nmos load inverter

simulate substrate bias

cmos xor gate

cmos nand gate

resistive load

transient characteristics