the end of eda - toward system design

8/10/2019 The End of EDA - Toward System Design

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The End of EDA

Toward System DesignRal Camposano

November, 2014


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The End of EDA

2

What we may be witnessing is not just the

commoditization of electronics,

or the passing of a particular period of

electronic design / EDA,but the end of electronic design / EDA as such:

that is, the end point of a technological evolution

and the universalization of the use of electronics

as the final form of intelligence in everything[1].[1] Paraphrasing Francis Fukuyamas essay "The End of History?" The National Interest, 1989


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The Free Lunch is (largely) Over

3Intel CPU Introductions (graph updated August 2009; article text original from December 2004)Source: The Free Lunch Is Over: A Fundamental Turn Toward Concurrency in Software

2014Fastest i7 3.6/4.0GHz, 150W

Fastest Xeon 3.4/3.7GHz, 155W


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4

Electronics $ 91

Other $120


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SW >$42 per Device

5


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Systems Companies Capturing Value

6

0

50

100

150

200

2005 2006 2007 2008 2009 2010 2011 2012 2013

Samsung

Apple

Microsoft

Amazon

Google

Intel

Facebook

Revenue

$B


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HW vs. SW

7

Patterson / HennessyThe HW / SW Interface Big Switch Networks

Wikipedia Xilinx

Software-Defined Satellite


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EDA also Evolved into (mostly) SW

Gen 1 1960-1980 CALMA, Computervision, Applicon, Zuken

Customized Workstation + Artwork Editing SW

DMV 1981-1988 Daisy, Mentor, Valid

Still substantial focus on Hardware sales

Gen 3 1988 Cadence (88 ECAD +SDA), Mentor, Synopsys (Optimal

Solutions 86)

Software

8


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EDA

$-

$1

$2

$3

$4

$5

$6

$7

$8

1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013

SNPS goes ratable

CDNS goes ratable

EDAC MSS

$B

9


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EDA

$-

$1

$2

$3

$4

$5

$6

$7

$8

1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013

SNPS goes ratable

CDNS goes ratable

EDAC MSS

$B

CAGR = 6%

10


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Buffets Valuation Indicator

11

Source: Board of Governors of the Federal Reserve System and U.S. Bureau of Economic Analysis

1950 1960 1970 1980 1990 2000 2010


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Gross World Product

Source: World Bank

$-

$10

$20

$30

$40

$50

$60

$70

$80

$T

12


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Gross World Product

Source: World Bank

$T

$-

$10

$20

$30

$40

$50

$60

$70

$80

CAGR = 6.1%

13


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Semiconductors

Source: SIA

$-

$50

$100

$150

$200

$250

$300

$350

$400

$-

$10

$20

$30

$40

$50

$60

$70

$80

$T $B

14


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Semi / WDC

0.0%

0.1%

0.2%

0.3%

0.4%

0.5%

0.6%

0.7%

15


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Semi / WDC

0.0%

0.1%

0.2%

0.3%

0.4%

0.5%

0.6%

0.7%

16

0.45%


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EDA

Source: EDAC

$-

$50

$100

$150

$200

$250

$300

$350

$400

$-

$1

$2

$3

$4

$5

$6

$7

$8

$B

17


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EDA

Source: EDAC

$-

$50

$100

$150

$200

$250

$300

$350

$400

$-

$1

$2

$3

$4

$5

$6

$7

$8

$B$B

18


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EDA / Semi

0.0%

0.5%

1.0%

1.5%

2.0%

2.5%

3.0%

3.5%

19

2.2%


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20


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21

6%


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22

Die

SoftwareSDK, IDE, compiler,

debugger, build,

source control

EDA

Package MCM, EM,Thermal, Mechanical

Board

Connector

PCB, EM,

Thermal, Mechanical

Sub-System Mechanical,

Thermal, EM

System Mechanical, CFD,

Thermal, EM

Ergonomics, sustainability, CO2emissions


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23

Package MCM, EM

Board

Connector

PCB, EM


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Hybrid Electromagnetic Simulation

3D3D2.5D

24


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Insertion Loss Return Loss

Near End Crosstalk Far End Crosstalk

Hybrid Mode

Hybrid

3D

Method Time Per Frequency Peak Memory

Full 3D 61 min 50 GB

Hybrid 2.D / 3D 6 min 5 GB

25


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Parallelism in EM Simulation

Layers: 8 Nets: 320 Ports: 1000

IBM Challenge Problem

Capacitance, Inductance of all nets

S-parameter extraction of 20 nets

26


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Capacitance Extraction of All NetsComputation Time Speedup

MS&S 8 cores 235 min 6x

RHS 80 machines 7.3 min 32x

Test Case upload 0.7 min

Result download 1.0 min

Peak Memory: 5.5 GB

RHS

Setup time = 1.8 min (serial)

p = (235-1.8) / 235 = 0.99234

Max Speedup =1

(1-p) +

p

n

= 50xN=80

Max Speedup =1

(1-p) +p

n

= 131x

n=

27


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Inductance Extraction of All PortsComputation Time Speedup

MS&S 8 cores 2741 min 6x

RHS 125 machines 50 min 55x



Peak Memory: 14 GB

RHS

Setup time: = 28 min (serial)

p = (2741-28) / 2741 = 0.98978

Max Speedup =1

(1-p) +

p

n

= 55xn=125

Max Speedup =1

(1-p) +p

n

= 98x

n=

28


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S-ParametersComputation Time Speedup

MS&S 8 cores 5954 min 6xRHS 5 machines

Freq 25x5 machines

70 min 3.4x

25x



Peak Memory: 11 GB

RHS

Setup time = 11.5 min (serial)

p = (119-11.5) / 119 = 0.8067

Max Speedup =

1

(1-p) +p

n

= 3.6xn=5

Max Speedup =1

(1-p) +p

n

= 10.3x

n=

29


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S-Parameters

Transmission

Reflection

30


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31

Licensing

nCloud supports a flexible licensing model,

ranging from hourly pay-as-you-go software-

as-a-service (SaaS) licensing to longer term

subscriptions such as monthly or annual.


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Simulation in the Cloud

32


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33

SDK IDE compiler


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34

Die

SoftwareSDK, IDE, compiler,

debugger, build,

source control

EDA

Package MCM, EM,Thermal, Mechanical

Board

Connector

PCB, EM,

Thermal, Mechanical

Sub-System Mechanical,

Thermal, EM

System Mechanical, CFD,

Thermal, EM

Ergonomics, sustainability, CO2emissions


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Software

35

Top10 Worldwide Software Vendors, Worldwide, 2012-2013 (Billions of Dollars)Source: Gartner (March 2014)

Rank

2013

Rank

2012 Vendor

2013

Revenue

2012

Revenue

2012-2013

Growth Rate (%)

1 1 Microsoft 65.7 62.0 6.0

2 3 Oracle 29.6 28.7 3.4

3 2 IBM 29.1 28.7 1.4

4 4 SAP 18.5 16.9 9.5

5 5 Symantec 6.4 6.4 -0.8

6 6 EMC 5.6 5.4 4.9

7 7 HP 4.9 5.0 -2.7

8 9 VMware 4.8 4.2 14.1

9 8 CA Technologies 4.2 4.3 -2.6

10 12 Salesforce.com 3.8 2.9 33.3Others 234.6 224.0 4.7

Total 407.3 388.5 4.8


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CAD / Simulation

36

Top5 Worldwide CAD Vendors, Worldwide, 2012-2013 (Billions of Dollars)Sources: JPR, Schnittger, Public Co.

Rank

2013

Rank

2012 Vendor

2013

Revenue

2012

Revenue

2012-2013

Growth Rate (%)

1 1 Dassault Systmes 2.6 2.5 1.8

2 2 Autodesk 2.3 2.2 4.1

3 3 Siemens PLM 1.8 1.7 7.5

4 4 PTC 1.3 1.3 3.0

5 5 Ansys .86 .80 7.9

Total 8.9 8.5 4.7

$B


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CAD / Simulation

37

$-

$1

$2

$3

$4

$5

$6

$7

$8

$9

$10

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013

$B


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$-

$1

$2

$3

$4

$5

$6

$7

$8

$9

$10

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013

CAD / Simulation$B

CAGR = 9.3%

38

fApplication

$ $


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39

Software

Die

Package

Board

Connector

Sub-System

System

pp

Development

Software

EDA

CAD

$9 / $407B

2.2%

$6.2 / $303B

2.0%

>$9 / >2T ?


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40


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Summary

Semiconductors and EDA have been

growing at the pace of GWP since 1996

Cost, complexity and functionality

continue to migrate to SW and system

EDA and CAD are poised for contact,

leading to system design

the end of eda - toward system design

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