track b- advanced esl verification - mentor

Advanced ESL Verification Refinement – From ESL to RTL

Guy MosheGeneral Manager

DCS

Mentor Graphics

May 4, 2011

2© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com

Abstract

ESL is quickly evolving as a methodology for designing a system using abstraction above RTL. This session covers an ESL Verification flow describing how ESL can be used to validate the HW/SW functionality, performance and power requirements. In addition, it addresses how the ESL environment can be reused at the SoC RTL block level verification phase, and at the system integration phase using emulation.

Advanced ESL Verification Refinement


Trends – Design Complexity Explosion

15 billion connected devices by 2015

Basic+ Smart+ Enhanced phones

Mobile processor clock speed > 1 GHz (32

nm)

Highly integrated: Audio, video, 3D graphics,

text

Requires long battery life

Marvell’s ARMADA 628 SoC

— Used for smartphones and tablets

— 1.5 GHz tri-core processor

— Dual stream 1080p 3D video

— 3D graphics performance (200M triangles/sec)

— Ultra-low-power, long battery life

ProcessorsCo Processor

Interconnect Fabric

Peripherals

DDRINTC DMA USB

Video

ADCWDTIMERUART

ETHERNET FLASH

2 billion phones by 2012



Design and Verification is a Struggle …

Source: The International Technology Roadmap for Semiconductors (ITRS), 2008 Update)

Cost of design tasks per technology

Power requirement vs. power trends

It’s a design and verification struggle It’s a power struggle



A Closer look on Multi-core Challenges

Multi-core architectures offer higher multi-tasking performance but introduce new design challenges— Scale for best MIPS per

Watt— Caching strategy— Port and Tune firmware

and operating system to the target hardware

— Migrate single-threaded applications to multi-core

— Balance HW and SW loads Designers need a platform

that enable fast compilation and configuration cycles through software and hardware alternatives

Interconnect Fabric

Peripherals

ADCWDTIMERUART

Video

DDR2DDR2ETH

DDRINTC DMA USB ETHERNET FLASH

CORE

I/cache D/cacheCache control

I/cache D/cache

COREAccelerator

Software



Introducing ESL Methodology

ESL allows you to reduce verification effort by:— Fast simulation of the

design functional spec in the system’s context

— Reducing RTL Verification effort by finding bugs early

— Validating Software integration with hardware even before RTL

— Reducing RTL block verification by using high level synthesis

Electronic System Level (ESL): A set of electronic hardware/software design methodologies using abstraction above RTL for designing systems on chips (SoCs), FPGAs and boardsElectronic System Level (ESL): A set of electronic hardware/software design methodologies using abstraction above RTL for designing systems on chips (SoCs), FPGAs and boards

Algorithmic

TLM

RTL

GATE 1 Day

1 Sec

Simulation Time Example



ESL Verification Flow – Why?

Transaction-level models (TLM) allow designers to:— Build software development and hardware architecture

exploration platforms before committing to RTL.— Manage the complexity of sophisticated large-scale SoC— Build and verify SoCs more quickly— Run orders of magnitude faster than RTL

Reuse the TLM as RTL verification testbench component

Standards-driven: OSCI TLM, SystemC, C++, OVM, UVM SystemVerilog



TLM System Verification:Validating & Debugging the SoC

Video

Interconnect Fabric

Peripherals

ADCWDTIMERUART

CORE


Accelerator

Verify Architecture and System Behavior— Integrated Behavior— System Level scenarios — SW Driven Tests— Data Driven Tests

Debug and comprehend your System— TLM code view— Process view— Transaction View— Event Tracing— Memory Profiling

Verify Architecture to Meet the Design Functional Spec



Architecting and Optimizing For Performance And Power

Interconnect Fabric

Peripherals

ADCWDTIMERUART

Video

DDR2DDR2ETH


CORE

I/cache D/cache

Cache control

I/cache D/cache

COREAccelerator

Partition HW & SW Define Bus

layering & arbitration

Define Cache & Memories layering & sizing

Optimize Data throughput and latencies

Analyze Power Profiles / Distribution



Software Hardware Interaction Critical

Multi-core architecture presents much tighter hardware software dependencies

Multiple applications may run with different performance and power profiles Dynamic Bandwidth

requirements The Mapping technique of

application threads to the cores will impact performance and power

Different code footprint depending on number of cores


Interconnect Fabric

Peripherals

ADCWDTIMERUART

Video

DDR2DDR2ETH


CORE

I/cache D/cache

Cache control

I/cache D/cache

COREAccelerator

AppApp.

App.

Operating System


HW/SW Tradeoff Analysis

Peripherals

ADCWDTIMERUART

ISSVideo

DDR2DDR2ETH

DDRINTC DMAUSB

ControllerETHERNET FLASH

Accelerator

USB

FW

OS

App

C/C++ execution on processor vs. HW acceleration

Common HW and SW representation (C/C++)

Explore power and timing affects in the System Context

HW Database



Creating a Virtual Prototype

Delivers a target HW model executable to the software team Integrate final application software against actual hardware

architecture Validate and debug software against early HW model before RTL Tune software to meet performance and power requirements

Virtual Prototype

End UserApplicationSoftware

End UserApplicationSoftware

Software Debuggers (GDB, ARM, EDGE)

Performance Power

AXI Bus

FPU

ROM

JPEGEncoder

CPU

RAM

CPU AXI I/F

Transaction Level Platform



HW Database

Running The Virtual Platform

HW Access & Analysis

SW IDE

HW / SW Partitioning Exploration

Peripherals

ADCWDTIMERUART

ISSVideo

DDR2DDR2ETH

DDRINTC DMAUSB


Accelerator

USB

FW

OS

App



Physical I/O

Peripherals

ADCWDTIMERUART

ISSVideo

DDR2DDR2ETH

DDRINTC DMAUSB


Accelerator

USB App Connect Virtual Model to physical I/O

USB, LAN IP Realistic packet load

generation

USB

Host PCUSB

Controller

USB Driver

Driv

er

USB App

USB Driver



SW engineer Use Case for multi-core

Explore various cache configurations Explore various software parallelization techniques Early test of data regularity for optimized cache access Early-stage power estimation for most efficient thread

partitioning

HW Database

Peripherals

ADCWDTIMERUART

ISSVideo

DDR2DDR2ETH

DDRINTC DMAUSB


Accelerator

USB

FW

OS

App

Single Core

Dual Core



TSMC ESL to RTL SoC Verification Vision


17© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.comAdvanced ESL Verification Refinement

TLM ARM Cortext-A9 platform

Drivers

Linux

MPEGUART

Cortex-A9


MPEGUART

Cortex-A9

TLM Platform with Power

Power

Show CPU Voltage/ Frequency Scaling

TSMCiPPA

Engine

TLM Domain Shut Down


TLM/RTL Hybrid Platform

Synthesized to RTL

Hybrid Extended Platform

SC/SVConnection

AXITransactors

MPEGRTLUART

RTLTransacto

r


TLM Design

Vista

MemoryTLM

Cortex A9ISS/TLM

(multi-core)

I/OSubsyste

m

AX

I B

us T

LMA

XI

Bus

TLM

InterruptController

RTL DesignVeloce

MPEGAXI Bridge

RTL

MPEGRTL

Sig

na

l Le

vel A

XI

Bu

sS

ign

al L

eve

l AX

I B

us

ESL Verification: From ESL to Acceleration Mixed TLM with accelerated RTL design

— RTL runs on Emulation at MHz speeds— Software runs on Multi-core Cortex A9 TLM model at 200 MIPS— Fast extended platform for validating SW against accelerated & accurate

HW model

20

AXIxMVC

Software

TLM Debug

SW Debug

RTL Debug


Hybrid TLM Platform with RTL EmulationAccelerated

On Emulation

Hybrid Extended Platform

Linux

SC/SV

VGAADAPTERRTL?

Uses AXIxMVC

MPEGRTL


Reusing TLM Models for OVM/UVM Block Verification



MPEGUART

Cortex-A9

Virtual Prototype w Linux

Link Linux

Link SW Dev Tool

Virtual Prototype


Summary

We have presented ESL methodology that enables— Creation of TLM Platforms— Virtual Prototyping and Software integration— Fast simulation speeds— Power Performance optimization— TLM verification at the system level— TLM/RTL refinement verification

We have presented a demonstration of ARM based reference flow

ESL and TLM will enable efficient design and prototyping of any future low-power multi-core SoC’s


track b- advanced esl verification - mentor

Education

esl verification flow

verification struggleits

tlm system verification

esl environment

power requirements

power strugglesource

different performance

d graphics performance