TRD Status Report

general status full scale prototype production

radiatorreadout chamberintegration issues

results from test beams gas system electronics

analog – pre-amplifier shaperdigital – ADC development, tracklet processorsystem integration – MCM, readout boardspowerdetector control system

Johannes P. Wessels – GSI Darmstadt

simulationsenvironmenttrigger performance, tracking

testbeam schedule milestones

General status

September `01 - technical design report submitted

November `01 – presented to the LHCC January `02 – recommended for approval by LHCC February `02 – approved by Research Board

because of the funding situation -> recommendation to build `short asymmetric´version (about 58%)

Actively seeking funds at the moment; Japanese have expressed interest to join the project and are in the process of requesting support.

Chamber design

pad plane with HEXCELL/CF backing

amplification region

drift region

radiator

First pad plane support Polish manufacturer (LHCb)

bottom side: flatness better than 100 microns

top side: flatness better than 300 microns

tolerances well within needs

First pad planes

size of ordered pieces: 1200 x 512 mm2 (200 µm thickness) need 3-4 pieces/chamber depending on length of chamber manufactured by OPTIPRINT, Switzerland still problems with handling

Bending of pad plane support

sandwich with aluminum frame taped to flat table

measurement of deflection of center and sides as function of overpressure

sandwich deforms exactly as calculated using a simple model for sandwich structures

maximum bending with respect to anode wires <220microns

Expected gas gain variation

gain varies linearly with bending of pad plane

for the maximum tolerated overpressure in the chamber about 15% gain variation is expected

additional wire sag not important for a large range in cathode wire tension

Radiator

CF-laminated `quilt´ structure of: 100 micron CF laminate Rohacell HF71 polypropylene fibers from Freudenberg LRP375BK

optimization of ROHACELL vs fiber thickness ongoing

have option to buy stock retained for Aachen for prototype developments

full production for ALICE TRD will be 80k€

Material for prototypes

goal is to build fully functional prototypesPolish CFK/HF71 (8mm) and 7 layers LRP375BK

- radiator finished including electrode - now testing for wire load and overpressure

AIK CFK/HF71 (8/6 mm) 7/8 layers LRP375BK - CFK on hand, fibers arrive by mid-April

Polish CFK/HF71 (6mm) with 8 layers LRP375BK - need to purchase raw materials and place order

Polish manufacturer provides thinner, smoother, and cheaper laminate – BUT sole supplier issue

Radiator detail

8mm ROHACELL HF71 coated with ~ 100 micron CF covered mith Al-Mylar

partially filled with Freudenberg fibers LRP375BK (ATLAS)

Full size radiator

laminated material purchased – radiator assembly by Muenster group

Detail during chamber assembly

assembly of first full scale prototype done in Heidelberg

Full scale prototype

largest chamber: 1200 x 1600 mm

Winding machine

machine currently under test at GSI

tensioning mechanism conditioned

full-size transfer frames delivered

will be moved to Heidelberg in April

Influence of wire tension on frames

Influence of wire tension on frames

deformation of sides about 130µm each

corresponds to maximum relaxation of wire tension by 13%

0

20

40

60

80

100

120

140

160

180

200

0 200 400 600 800 1000 1200 1400 1600 1800

position along z (mm)

de

fle

cti

on

(µ

m)

TDR +10%

TDR +30%

TDR -12%

red line denotes load according to TDR

Gas feed-through - design

pressure drop for 10 chambers< 0.05 mbar

2 feed throughs per chamber10 chambers per circuit

Gas feed-through

•leakage has been tested with small prototypes•misalignment of chambers was pushed to 4 degrees between faces

at 10l/h flow and 10ppm oxygen -> full TRD would loose 0.027l/h due to seals (TDR < 0.5l/h)approx. 1000 CHF/yr

Integration into space frame

Revised super module design

Rollers

rollers now attached to L-profiles welded to space frame

reduces space necessary for support

increases stiffness of thin supermodules

same gadgets needed on installation tool

Results from 2001 testbeam

resolution of the `good´ xenon - `bad´ xenon story

momentum scan to evaluate pion rejection for various compositions of radiator materials

position resolution and angular resolution for tracking

Testbeam setup

TRD signals: pions, electrons

Good Xenon – Bad Xenon

different bottles of Xe show very different average pulse height distributions in drift region

finally managed to resolve this

long-standing problem traced to minuscule

contaminations of VERY electronegative components

<0.1ppm CF4

0.08ppm C2F6

0.8ppm O2

0.68ppm SF6 (!)

suppliers now aware of this

Status of gas system

test system with purification and recuperation operational

molecular sieves retain CO2

because of small volumes used so far, recuperation only performed off-line

test system modified; now includes buffer vessel for regulating small volumes (compressor can handle full detector -> 27m3)

system including recuperation will be used in the stack test in Fall 2002

Pion efficiency

CERN measurements scaled to reproduce GSI data at 1 GeV/c for identical radiator

pion sample still contains some (soft?) electrons (next slide)

pion rejection shown to not deteriorate for higher momenta

thick carbon fiber laminate 300 microns decreases rejection by factor 2-3. Still at 1% in relevant momentum range

new production uses only about 100 microns

Electron pion spectra

Simulation + Data - GSI

Data (CERN T10 + GSI)

Local track reconstruction

Tracking resolution

ALICE operational point at S/N = 30-40 difference in angular resolution is an artifact due to slightly

different length of the drift region in the two test chambers

Tracking resolution (B-field)

test setup at GSI with large coils

soft delta electrons curl up in magnetic field

improved point and angular resolution

Lorentz angle for Xenon

exact knowledge of Lorentz angle necessary for precise track reconstruction

data in literature not consistent

within limits posed by the precise knowledge of the CO2 content values agree with MAGBOLTZ

TRD electronics chain

Preamplifier status

Parameter TDR Simulation

No. channels 1 200 000 --

Noise (ENC) 1000 e 720 e (20pF)

Conversion Gain

12.2 mV/fC 12.5 mV/fC

Shaping time about 120 ns about 130 ns

Non-linearity < 1% < 0.25%

Power consumption

< 20 mW/ch 12.8 mW/ch

output variationswith T, Vdda

-- <0.73% (20 deg)<0.09% (200mV)

Chip area -- 22 mm2

3rd chip submitted end of January

expected back end of March

possibly last iteration

increased size due to fully differential design

Footprint of preamplifier

18 fourth order pre-amp shapers with differential outputs (21)

external references to adjust to range of ADCs digital test structure for chip verification size of chip: 3030 µm x 7280 µm

Evaluation of PASA

complete evaluation prepared; chip expected back in two weeks

some results from simulationsfull signal in center channel50% signal in adjacent pads

-> produces cross talk on <10-5 level in neighboring channels

full corner analysisonly small yield expected outside specifications (mainly leading to too short shaping time)gain variations tolerable

Digital chip - recent changes & developments

Conceptual Design Review conducted in early January complete design now for 0.18µm UMC process tail cancellation network now baseline design link width reduced to D8+P+Spare double data rate

giving up on dynamic error correction (Hamming)implementation of one spare signal allowing to multiplex out stuck bits (maximum 2 per link)

readout tree simplified configuration tree fully operable in FPGAs (2 nodes tested;

currently implementing Linux interface) MIMD CPU (1 node) operable in FPGA FPGA CPU boots UCLinux for Slow Control LVDS Rx and Tx implement power down mode now (wake-up

time ~500 ps) use of ALTRO chip as 16-channel ADC from TPC (test/fall back)

ADC – Univ. Kaiserslautern

D Q D Q

D Q D Q

...

...

S hiftreg iste r + D ecoder

O utpu t-La tches

...

...

B 9 B 0

C on tro lle r(sha red w itho ther A D C s)

Load

D R

StrobeA Z(S am p le)

2 -P hase-genera tor,Leve lsh ift

+1

-1

+1

-1

-1

-1

A m p l i f i e r b l o c k C o m p a r a t o r s

I N + I N -

V o l t a g e r e f e r e n c e( s h a r e d w i t h o t h e rA D C s )

3 , 3 V

1 , 8 V

1 , 8 V

G N D

G N D

G N D

1 2 0 M H z 1 0 M H z( S a m p l e - E N )

A d j u s t( 5 b i t s )

c l o c k

d ig ita lp a r t

a n a lo gp a r t

s w itc h e s

s i n g l e A D C

V r e f +

V r e f -

V c m

V c e n t e r

A d j u s t ( 5 b i t s )

d i g i t a l i n t e r f a c e

a n a l o g i n t e r f a c e

Parameter Value

Sampling Rate 10 MSpS

Resolution 10 Bits

Power Consumption 5 mW

Max. INL 1 LSB

Input signal BW 5 MHz

Diff. Input Range +/- 1V

Chip Area 0.2 mm²

Converter Principle cyclic

PAD layout of TRAP1 chipNI_P0_D7+

NI_P0_D7-

NI_P1_D5+

NI_P1_D5-

NI_P1_D6+

NI_P1_D6-

NI_P1_D7+

NI_P1_D7-

NI_P1_D8+

NI_P1_D8-

NI_P1_D9+

NI_P1_D9-

NI_P1_CTRL+

NI_P1_CTRL-

NI_P1_STRB+

NI_P1_STRB-

NI_P1_PREo+

NI_P1_PREo-

NC

NC

SER1_DIN+

SER1_DIN-

SER1_DOUT+

SER1_DOUT-

NC

NC

RST_n

OUT_RNG

NC

NC

NC

VCC

GND

NI_P4_D2+

NI_P4_D2-

VCC

GND

NI_P4_D3+

NI_P4_D3-

VCC

GND

NI_P4_D4+

NI_P4_D4-

NI_P4_D5+

NI_P4_D5-

VCC

GND

NI_P4_D6+

NI_P4_D6-

VCC

GND

NI_P4_D7+

NI_P4_D7-

NI_P4_D8+

NI_P4_D8-

VCC

GND

NI_P4_D9+

NI_P4_D9-

VCC

GND

NI_P4_CTRL+

NI_P4_CTRL-

VCC

GND

NI_P4_STRB+

NI_P4_STRB-

NI_P4_PREi+

NI_P4_PREi-

VCC

GND

NC

NI_P2_D1+

NI_P2_D1-

NI_P2_D0+

NI_P2_D0-

NC

NI_P2_CLKo+

NI_P2_CLKo-

NC

NI_P3_CLKo+

NI_P3_CLKo-

NC

NI_P3_D0+

NI_P3_D0-

NI_P3_D1+

NI_P3_D1-

NI_P3_D2+

NI_P3_D2-

NI_P3_D3+

NI_P3_D3-

NI_P3_D4+

NI_P3_D4-

NI_P3_D5+

NI_P3_D5-

NI_P3_D6+

NI_P3_D6-

NI_P3_D7+

NI_P3_D7-

NI_P3_D8+

NI_P3_D8-

NI_P3_D9+

NI_P3_D9-

NI_P3_CTRL+

NI_P3_CTRL-

NI_P3_STRB+

NI_P3_STRB-

NI_P3_PREo+

NI_P3_PREo-

NC

VCCGNDNI_P0_ D5+NI_P0_ D5-VCCGNDNI_P0_ D4+NI_P0_ D4-VCCGNDNI_P0_ D3+NI_P0_ D3-VCCGNDNI_P0_ D2+NI_P0_ D2-NI_P0_ D1+NI_P0_ D1-VCCGNDNI_P0_ D0+NI_P0_ D0-VCCGNDNI_P0_C LKo+NI_P0_C LKo-VCCGNDNI_P4_C LKi+NI_P4_C LKi-VCCGNDNI_P4_ D0+NI_P4_ D0-VCCGNDNI_P4_ D1+NI_P4_ D1-VCCGND

VCC

GND

NI_P0_D8+

NI_P0_D8-

NI_P0_D9+

NI_P0_D9-

VCC

GND

NI_P0_CTRL+

NI_P0_CTRL-

VCC

GND

NI_P0_STRB+

NI_P0_STRB-

VCC

GND

NI_P0_PREo+

NI_P0_PREo-

VCC

GND

SER0_DIN+

SER0_DIN-

SER0_DOUT+

SER0_DOUT-

VCC

GND

TDO

TDI

TMS

TCK

VCC

GND

VCCGNDCLK_PLL _INCLK_PLL _INVCCGNDADCM0 _D9ADCM0 _D7ADCM0 _D5ADCM0 _D3VCCADC_C LKGNDADCM2 _D1ADCM2 _D3ADCM2 _D5ADCM2 _D7VCCGNDADCM3 _D9ADCM3 _D7ADCM3 _D5ADCM3 _D3VCCGNDADCM1 _D1ADCM1 _D3ADCM1 _D5ADCM1 _D7VCCGNDADC_S EL0

PLL_LOC KEDPLL_RE SETSEL_C LKPA_SS TRPA_SC LKPA_SD ATADCM0 _D8ADCM0 _D6ADCM0 _D4ADCM0 _D2ADCM0 _D1ADCM0 _D0ADCM2 _D0ADCM2 _D2ADCM2 _D4ADCM2 _D6ADCM2 _D8ADCM2 _D9ADCM3 _D8ADCM3 _D6ADCM3 _D4ADCM3 _D2ADCM3 _D1ADCM3 _D0ADCM1 _D0ADCM1 _D2ADCM1 _D4ADCM1 _D6ADCM1 _D8ADCM1 _D9ADC_S EL1

ADC

PLLNI_P0_ D6+NI_P0_ D6-NI_P1_ D4+NI_P1_ D4-NI_P1_ D3+NI_P1_ D3-NI_P1_ D2+NI_P1_ D2-NI_P1_ D1+NI_P1_ D1-NI_P1_ D0+NI_P1_ D0-NCNI_P1_C LKo+NI_P1_C LKo-NCNI_P2_P REo+NI_P2_P REo-NI_P2_S TRB+NI_P2_S TRB-NI_P2_C TRL+NI_P2_C TRL-NI_P2_ D9+NI_P2_ D9-NI_P2_ D8+NI_P2_ D8-NI_P2_ D7+NI_P2_ D7-NI_P2_ D6+NI_P2_ D6-NI_P2_ D5+NI_P2_ D5-NI_P2_ D4+NI_P2_ D4-NI_P2_ D3+NI_P2_ D3-NI_P2_ D2+NI_P2_ D2-NC

NORTH

SOUTH

EAST

WEST Output port

Input port

Input port

Input port

Input port

5050 µm

5050

µm

1,3x1.3 mm

AD

C

4950 µm

3150 µm63 PADs

Corner

500µm

Corner

500µm

3950

µm

79 P

AD

s

3950 µm79 PADs

3150

µm

63 P

AD

s 284 PADs total14,96 mm² (excl ADC,and PAD area)

Corner

500µm

total area 25mm2

32 power/GND padsmerger MCMs require only single pad ring

MIMD Processor

screen shot offull layout ofMIMD processor

MCM footprint

BGA432 package432 pins (4 rows, 31 pads)grid 1.27mm x 1.27 mmdimensions roughly 40x40 mm2

few external components

contains 18ch preamp 21 ADCs (ALTRO) tracklet processor controls

LVDS design of readout board

Status of simulation software

geometry follows latest design detailed geometry of MCMs and

cooling included supermodule support structure

included; rails, services soon to come

hit compression from TPC included

tilted pad option included adapted pad response functions time response function included digital filter tail cancellation

included

MCM detail

Detail of simulated geometry

New digits display available

allows to superimposedigits from different events

Tracking

trigger performance now checked for tilted pads

fast simulations -> parameterization of response will done

global tracking strategy for all detectors IST, TPC, TRD now using Kalman filter

still some problems with tilted pads for electrons special treatment of

Bremsstrahlung needs to be implemented

electron identification and pion rejection using transition radiation and dE/dx signals need to be provided for electron tracking strategy

Future use of testbeams

2002 – 12 days (performance)stack test (at least three layers)momentum dependence of pion rejectionfinal preamp and tracklet processor on MCMfinal gas systemcooling and DCS test systems

2003 – 9 days (1/3 performance, 2/3 quality assurance)

full stack test – multi-hit capabilitytrigger performance evaluationtest of readout systemcheck of cooling and DCS systems

2004 – 8 days (1/2 calibration, 1/2 quality assurance)

several full stack testshigh statistics measurement of pion and electron spectra up to highest momenta (6 GeV/c)test of global tracking unit (GTU)test of calibration scheme

2005 – 7 days (calibration)calibration of several stacks including full momentum scancommissioning of GTU

Milestones

12-01: digital chip engineering design reviewdone in January; concept considered appropriate yet challenging; some suggestions already incorporated for submission

01-02: 3rd MPW run submission of PASAdate has been met, chips expected back in about two weeks

04-02: 1st submission of digital chip TRAP1actual submission date will be April, 17; contains track let processor, 3 ADCs, configuration tree, separate inputs for use with external ADCs

05-02: engineering design review of chamber designforeseen for end of May; date can be met if all pending tests go well

Dates for production milestones will need to be revisited if change in overall schedule will be announced