vlsi - chp05

Cressler, J.D.“SiGe Technology”The VLSI Handbook.Ed. Wai-Kai ChenBoca Raton: CRC Press LLC, 2000

© 2000 by CRC PRESS LLC

5SiGe Technology

5.1 Introduction 5.2 SiGe Strained Layer Epitaxy5.3 The SiGe Heterojunction Bipolar Transistor (HBT)5.4 The SiGe Heterojunction Field Effect

Transistor (HFET)5.5 Future Directions

5.1 Introduction

The concept of bandgap engineering has been used for many years in compound semiconductors suchas gallium arsenide (GaAs) and indium phosphide (InP) to realize a host of novel electronic devices. Abandgap-engineered transistor is compositionally altered in a manner that improves a specific devicemetric (e.g., speed). A transistor designer might choose, for instance, to make a bipolar transistor thathas a GaAs base and collector region, but which also has a AlGaAs emitter. Such a device has electricalproperties that are inherently superior to what could be achieved using a single semiconductor. In additionto simply combining two different materials (e.g., AlGaAs and GaAs), bandgap engineering often involvescompositional grading of materials within a device. For instance, one might choose to vary the Al contentin an AlGaAs/GaAs transistor from a mole fraction of 0.4 to 0.6 across a given distance within the emitter.

Device designers have long sought to combine the bandgap engineering techniques enjoyed incompound semiconductors technologies with the fabrication maturity, high yield, and hence low costassociated with conventional silicon (Si) integrated circuit manufacturing. Epitaxial silicon-germanium(SiGe) alloys offer considerable potential for realizing viable bandgap-engineered transistors in the Simaterial system. This is exciting because it potentially allows Si electronic devices to achieve perfor-mance levels that were once thought impossible, and thus dramatically extends the number of high-performance circuit applications that can be addressed using Si technology. This chapter reviews therecent progress in both SiGe heterojunction bipolar transistor (HBT) technology and SiGe field effecttransistor (FET) technology.

5.2 SiGe Strained Layer Epitaxy

Si and Ge, being chemically compatible elements, can be intermixed to form a stable alloy. Unfortunately,however, the lattice constant of Si is about 4.2% smaller than that of Ge. The difficulties associated withrealizing viable SiGe bandgap-engineered transistors can be traced to the problems encountered ingrowing high-quality, defect-free epitaxial SiGe alloys in the presence of this lattice mismatch. Forelectronic applications, it is essential to obtain a SiGe film that adopts the same lattice constant as theunderlying Si substrate with perfect alignment across the growth interface. In this case, the resultant SiGealloy is under compressive strain. This strained SiGe film is thermodynamically stable only under anarrow range of conditions that depend on the film thickness and the effective strain (determined by

John D. CresslerAuburn University

© 2000 by CRC Press LLC

the Ge concentration).1 The critical thickness below which the grown film is unconditionally stabledepends reciprocally on the effective strain (Fig. 5.1). Thus, for practical electronic device applications,SiGe alloys must be thin (typically <100–200 nm) and contain only modest amounts of Ge (typically<20–30%). It is essential for electronic devices that the SiGe films remain thermodynamically stable sothat conventional Si fabrication techniques such as high-temperature annealing, oxidation, and ionimplantation can be employed without generating defects.

From an electronic device viewpoint, the property of the strained SiGe alloy that is most often exploitedis the reduction in bandgap with strain and Ge content (roughly 75 meV per 10% Ge).2 This band offsetappears mostly in the valence band, which is particularly useful for realizing n-p-n bipolar transistorsand p-channel FETs.3 While these band offsets are modest compared to those that can be achieved inIII–V semiconductors, the Ge content can be compositionally graded to produce local electric fields thataid carrier transport. For instance, in a SiGe HBT, the Ge content might be graded from 0 to 15% acrossdistances as short as 50 to 60 nm, producing built-in drift fields as large as 15 to 20 kV ⋅ cm–1. Such fieldscan rapidly accelerate the carriers to scattering-limited velocity (1 × 107 cm ⋅ s–1), thereby improving thetransistor frequency response. Another benefit of using SiGe strained layers is the enhancement in carriermobility. This advantage will be exploited in SiGe channel FETs, as discussed below.

Epitaxial SiGe strained layers on Si substrates can be successfully grown today by a number of differenttechniques, including molecular beam epitaxy (MBE), ultra-high vacuum/chemical vapor deposition(UHV/CVD), rapid-thermal CVD (RTCVD), atmospheric pressure CVD (APCVD), and reduced pres-sure CVD (RPCVD). Each growth technique has advantages and disadvantages, but it is generally agreedthat UHV/CVD,4 has a number of appealing features for the commercialization of SiGe integrated circuits.The features of UHV/CVD that make it particularly suitable for manufacturing include: (1) batchprocessing on up to 16 wafers simultaneously, (2) excellent doping and thickness control on large (e.g.,200 mm) wafers, (3) very low background oxygen and carbon concentrations, (4) compatibility withpatterned wafers and hence conventional Si bipolar and CMOS fabrication techniques, and (5) the abilityto compositionally grade the Ge content in a controllable manner across short distances. The experimentalresults presented in this chapter are based on the UHV/CVD growth technique as practiced at IBMCorporation, and are representative of the state-of-the-art in SiGe technology.

FIGURE 5.1 Effective thickness versus effective strain for SiGe strained layer epitaxy. Shown are a theoretical stabilitycurve (Matthews-Blakeslee), and an empirical curve for UHV/CVD SiGe epitaxy. The symbols represent actual filmsused in UHV/CVD SiGe HBTs.


5.3 The SiGe Heterojunction Bipolar Transistor (HBT)

The SiGe HBT is by far the most mature Si-based bandgap-engineered electronic device.5 The first SiGeHBT was reported in 1987,6,7 and began commercial production in 1998. Significant steps along the pathto manufacturing included the first demonstration of high-frequency (75 GHz) operation of a SiGe HBTin a non-self-aligned structure in early 1990.8 This result garnered much attention worldwide becausethe performance of the SiGe HBT was roughly twice what a state-of-the-art Si BJT could achieve (Fig.5.2). The first fully integrated, self-aligned SiGe HBT technology was demonstrated later in 1990,9 thefirst fully integrated 0.5-µm SiGe BiCMOS technology (SiGe HBT + Si CMOS) in 1992,10 and SiGe HBTswith frequency response above 100 GHz in 1993 and 1994.11,12 A number of research laboratories aroundthe world have demonstrated robust SiGe HBT technologies, including IBM,13–17 Daimler-Benz/TEMIC,18–21 NEC,22–24 and Siemens.25 More recent work has begun to focus on practical SiGe HBTcircuits for radio-frequency (RF) and microwave applications.26–28

Because the intent in SiGe technology is to combine bandgap engineering with conventional Sifabrication techniques, most SiGe HBT technologies appear very similar to conventional Si bipolartechnologies. A typical device cross-section is shown in Fig. 5.3. This SiGe HBT has a planar, self-alignedstructure with a conventional polysilicon emitter contact, silicided extrinsic base, and deep- and shallow-trench isolation. A 3-5 level, chemical-mechanical-polishing (CMP) planarized, W-stud, AlCu CMOSmetalization scheme is used. The extrinsic resistive and capacitive parasitics are intentionally minimizedto improve the maximum oscillation frequency (fmax) of the transistor. Observe that the Ge is introducedonly into the thin base region of the transistor, and is deposited with a thickness and Ge content thatensures the film is thermodynamically stable (examples of real SiGe HBT profiles are shown as symbolsin stability space in Fig. 5.1). The in situ boron-doped, graded SiGe base is deposited across the entirewafer using the ultra-high vacuum/chemical vapor deposition (UHV/CVD) technique. In areas that arenot covered by oxide, the UHV/CVD film consisting of an intrinsic-Si/strained boron-doped SiGe/intrin-sic-Si stack is deposited as a perfect single-crystal layer on the Si substrate. Over the oxide, the depositedlayer is polycrystalline (poly) and will serve either as the extrinsic base contact of the SiGe HBT, the poly-on-oxide resistor, or the gate electrode of the Si CMOS devices. The metallurgical base and single-crystalemitter widths range from 75 to 90 nm and 25 to 35 nm, respectively. A masked phosphorous implantis used to tailor the intrinsic collector profile for optimum frequency response at high current densities.

FIGURE 5.2 Transistor cutoff frequency as a function of publication date comparing Si BJT performance and thefirst SiGe HBT result.


A conventional deep-trench/shallow-trench bipolar isolation scheme is used, as well as a conventionalarsenic-doped polysilicon emitter layer. This approach ensures that the SiGe HBT is compatible withcommonly used (low-cost) bipolar/CMOS fabrication processes. A typical doping profile measured bysecondary ion mass spectroscopy (SIMS) of the resultant SiGe HBT is shown in Fig. 5.4.

The smaller base bandgap of the SiGe HBT can be exploited in three major ways, and is best illustratedby examining an energy band diagram comparing a SiGe HBT with a Si BJT (Fig. 5.5). First, note thereduction in base bandgap at the emitter–base junction. The reduction in the potential barrier at theemitter–base junction in a SiGe HBT will exponentially increase the collector current density and, hence,current gain (β = JC/JB) for a given bias voltage compared to a comparably designed Si BJT. Comparedto a Si BJT of identical doping profile, this enhancement in current gain is given by:

(5.1)

FIGURE 5.3 Schematic cross-section of a self-aligned UHV/CVD SiGe HBT.

FIGURE 5.4 Secondary ion mass spectroscopy (SIMS) doping profile of a graded-base SiGe HBT.

JC SiGe,

JC Si,-------------

βSiGe

βSi

---------- γη∆Eg Ge, grade( ) kT e

∆Eg Ge, 0( ) kT⁄⁄

1 e∆Eg Ge, grade( ) kT⁄–

–-------------------------------------------------------------------------= =


where γ = NCNV (SiGe)/NCNV(Si) is the ratio of the density-of-states product between SiGe and Si, andη = Dnb(SiGe)/Dnb(Si) accounts for the differences between the electron and hole mobilities in the base.The position dependence of the band offset with respect to Si is conveniently expressed as a bandgapgrading term (∆Eg,Ge(grade) = ∆Eg,Ge(Wb) – ∆Eg,Ge(0)). As can be seen in Fig. 5.6, which compares themeasued Gummel characteristics for two identically constructed SiGe HBTs and Si BJTs, these theoreticalexpectations are clearly borne out in practice.

FIGURE 5.5 Energy band diagram for both a Si BJT and a graded-base SiGe HBT.

FIGURE 5.6 Measured current/voltage characteristics of both SiGe HBT and Si BJT with a comparable doping profile.


Secondly, if the Ge content is graded across the base region of the transistor, the conduction bandedge becomes position dependent (refer to Fig. 5.5), inducing an electric field in the base that acceleratesthe injected electrons. The base transit time is thereby shortened and the frequency response of thetransistor is improved according to:

(5.2)

Figure 5.7 compares the measured unity gain cutoff frequency (fT) of a SiGe HBT and a comparablyconstructed Si BJT, and shows that an improvement in peak fT of 1.7X can be obtained with relativelymodest Ge profile grading (0–7.5% in this case). More recent studies demonstrate that peak cutofffrequencies in excess of 100 GHz can be obtained using more aggressively designed (although still stable)Ge profiles12 (see Fig. 5.8).

The final advantage of using a graded Ge profile in a SiGe HBT is the improvement in the outputconductance of the transistor, an important analog design metric. For a graded-base SiGe HBT, the Earlyvoltage (a measure of output conductance) increases exponentially compared to a Si BJT of comparabledoping, according to:

(5.3)

In essence, the position dependence of the bandgap in the graded-base SiGe HBT weights the base profiletoward the collector region, making it harder to deplete the base with collector-base bias, hence yieldinga larger Early voltage. A transistor with a high Early voltage has a very flat common-emitter outputcharacteristic, and hence low output conductance. For the device shown in Fig. 5.6, the Early voltageincreases from 18 V in the Si BJT to 53 V in the SiGe HBT, a 3X improvement.

SiGe HBTs have been successfully integrated with conventional high-performance Si CMOS to realizea SiGe BiCMOS technology.15 The SiGe HBT and ac performance in this SiGe BiCMOS technology is

FIGURE 5.7 Measured cutoff frequency as a function of bias current for both SiGe HBT and Si BJT with acomparable doping profile.

τb SiGe,

τb Si,-------------

fT Si,

fT SiGe,-------------

2η--- kT

∆Eg Ge, grade( )----------------------------------

1 1 e∆Eg Ge, grade( ) kT⁄–

–∆Eg Ge, grade( ) kT⁄---------------------------------------------–= =

VA SiGe,

VA Si,--------------- e

∆Eg Ge, grade( ) kT⁄ 1 e∆Eg Ge, grade( ) kT⁄–

–∆Eg Ge, grade( ) kT⁄( )

-------------------------------------------------=


shown in Fig. 5.9, and is not compromised by the addition of the CMOS devices. Table 5.1 shows thesuite of resultant elements in this SiGe BiCMOS technology. Two SiGe HBTs are available, one with areduced collector implant and hence higher BVCEO (5.3 V vs. 3.3 V) that is suitable for RF powerapplications. Table 5.2 gives the typical SiGe HBT device parameters at 300K.

Bandgap-engineered SiGe HBTs have other attractive features that make them ideal candidates forcertain circuit applications. For instance, Si BJT technology is well known to have superior low-frequencynoise properties compared to compound semiconductor technologies. Low-frequency noise is often amajor limitation for RF and microwave systems because it directly limits the spectral purity of thetransmitted signal. Recent work suggests that SiGe HBTs have low-frequency properties as good as orbetter than Si BJTs, superior to that obtained in AlGaAs/GaAs HBTs and Si CMOS (Fig. 5.10).29,30 The

FIGURE 5.8 Cutoff frequency as a function of bias current for an aggressively designed UHV/CVD SiGe HBT.

FIGURE 5.9 Cutoff frequency, maximum oscillation frequency, and small-signal base resistance for a small-geom-etry, state-of-the-art SiGe HBT.


broadband (RF) noise in SiGe HBTs is competitive with GaAs MESFET technology and superior to SiBJTs. In addition, SiGe HBTs have recently been shown to be very robust with respect to ionizing radiation,an important feature for space-based electronic systems.31,32 Finally, cooling enhances all of the advantagesof a SiGe HBT. In striking contrast to a Si BJT, which strongly degrades with cooling, the current gain,Early voltage, cutoff frequency, and maximum oscillation frequency (fmax) all improve significantly as thetemperature drops.33–35 This means that the SiGe HBT is well-suited for operation in the cryogenicenvironment (e.g., 77K), historically the exclusive domain of Si CMOS and III–V compound semicon-ductor technologies. Cryogenic electronics is in growing use in both military and commercial applicationssuch as space-based satellites, high-sensitivity instrumentation, high-TC superconductors, and futurecryogenic computers.

5.4 The SiGe Heterojunction Field Effect Transistor (HFET)

The effective carrier mobility (µeff ) is the fundamental parameter that limits the speed of field effecttransistors (FETs), and SiGe bandgap engineering can be used in two principal ways to significantlyimprove the mobility and, hence, the speed of the device. First, the valence band offset associated withSiGe can be used to spatially confine carriers such that they are effectively removed from the Si/SiO2

interface. The surface roughness scattering associated with the Si/SiO2 interface degrades the mobilityin a conventional MOSFET, particularly at high gate bias. If, in addition, the holes are confined to aregion of the semiconductor that is intentionally left undoped, the result is a reduction in ionizedimpurity scattering and, hence, further increase in mobility.2 This is exactly the approach taken inbandgap-engineered compound semiconductor FETs known as HEMTs (high electron mobility tran-sistor). Second, the strain associated with SiGe epitaxy is known to lift the degeneracy of the light andheavy hole valence bands, resulting in a reduced hole effective mass and hence higher hole mobility.3

TABLE 5.1 Elements in IBM’s SiGe BiCMOS Technology

Element CharacteristicsStandard SiGe HBT 47 GHz fT at BVCEO = 3.3VHigh-breakdown SiGe HBT 28 GHz fT at BVCEO = 5.3VSi CMOS 0.36 mm Leff for 2.5 V VDD

Gated lateral pnp 1.0 GHz fT

Polysilicon resistor 342 Ω/Ion-implanted resistor 1,600 Ω/Thin-oxide decoupling capacitor 1.52 fF/µm2

MIM precision capacitor 0.70 fF/µm2

Inductor (6-turn) 10 nH with Q = 10 at 1.0 GHzSchottky barrier diode 213 mV at 100 µAp-i-n diode 790 mV at 100 µAVaractor diode 810 mV at 100 µAESD diode 1.2 kV

TABLE 5.2 Typical Parameters for a SiGe HBT with AE = 0.5 × 2.5 µm2. All ac Parameters Were Measured at VCB = 1.0V and fmax was Extracted Using MAG.

Parameter Standard SiGe HBT High-BVCEO SiGe HBTPeak β 113 97VA (V) 61 132βVA (V) 6,893 12,804Peak fT (GHz) 48 28rbb at peak fT (Ω) 80 N/APeak fmax (GHz) 69 57BVCEO (V) 3.3 5.3BVEBO (V) 4.2 4.1Peak fT × BVCEO (GHz V) 158 143


Because it is the hole mobility that is improved in strained SiGe, and the valence band offset can beused to confine these holes, the p-channel FET (pFET) is the logical device to pursue with SiGe bandgapengineering. A SiGe pFET with an improved hole mobility is particularly desirable in CMOS technologybecause the conventional Si pFET has a mobility that is about a factor of two lower than the Si nFETmobility. This mobility asymmetry between pFET and nFET in conventional Si CMOS technologyrequires a doubling of the pFET gate width, and thus a serious real estate penalty, to obtain properswitching characteristics in the CMOS logic gate. If SiGe can be used to equalize the pFET and nFETmobilities, then substantial area advantages can be realized in CMOS logic gates, and tighter packingdensities achieved.

It is interesting to note that despite the fact that the SiGe HBT is the most commercially mature SiGedevice, the first SiGe FET (actually a HEMT structure) predates the first SiGe HBT by one year, havingbeen first reported in 1986.36,37 A number of different SiGe pFET designs have been successfullydemonstrated38–43 with improvements in mobility as high at 50% at 0.25-µm gate lengths.40 Figure 5.11shows perhaps the simplest configuration of a SiGe pFET, which consists of a SiGe hole channel buriedunderneath a thin Si cap layer and the conventional thermal oxide.44,45 In this case, the entire device isfabricated on a silicon-on-sapphire substrate to improve microwave performance. Significant mobilityadvantage can be realized over a comparable Si pFET (Fig. 5.12).

Because a complementary circuit configuration offers many advantages from a power dissipationstandpoint, the realization of n-channel SiGe devices is highly desirable. Strictly speaking, this is notpossible in strained SiGe on Si substrates because only a valence band offset is available and the electronscannot be confined as in the SiGe pFET. Fortunately, however, recent work46–51 using strained Si onrelaxed SiGe layers has proven particularly promising because it provides a conduction band offset andenhanced electron mobility compared to Si.

The fabrication of strained Si nFETs on relaxed SiGe layers is, in general, more complicated thanfabricating strained SiGe pFETs in Si substrates. For the strained Si nFET, a graded SiGe buffer layer isused to reduce and confine the dislocations associated with the growth of relaxed SiGe layers.46 Usingthis technique, both strained Si nFETs and strained SiGe pFETs can be jointly fabricated to form a Si-based heterojunction CMOS (HCMOS) technology. Figure 5.13 shows a schematic cross-section of sucha Si/SiGe HCMOS technology,51 and represents the state-of-the-art in the field of Si/SiGe HCMOS.Observe that the conducting channels of both transistors are grown in a single step (using UHV/CVDin this case), and electron and hole confinement occurs in the strained SiGe and strained Si for the pFETand nFET, respectively. In this technology, both the pFET and nFET are realized in a planar structure,

FIGURE 5.10 Low-frequency noise spectra of SiGe HBT and a conventional Si nFET of identical geometry.


and are expected to show substantial improvements in performance over conventional Si CMOS. Withlayer and doping profile optimization, the parasitic surface channel (which degrades mobility) can beminimized. Simulation results of anticipated circuit performance indicate that substantial improvements(4 to 6X) in power-delay product over conventional Si CMOS can be obtained using Si/SiGe HCMOStechnology at 0.2-µm effective gate length.

5.5 Future Directions

The future developments in SiGe electronic devices will likely follow two paths. The first path will betoward increased integration and scaling of existing SiGe technologies. There is already a clear trendtoward integrating SiGe HBTs with conventional Si CMOS to form a SiGe BiCMOS technology.14,15

FIGURE 5.11 Schematic cross-section of SiGe pFET on silicon-on-sapphire (SOS).

FIGURE 5.12 Effective mobility as a function of gate drive comparing SiGe pFETs on SOS and conventional SipFETs on SOS.


Eventually, one would like to merge SiGe HBTs, Si CMOS, Si/SiGe HCMOS, and SiGe photonic deviceson the same chip to provide a complete solution for future RF and microwave electronic and optoelec-tronic transceivers containing precision analog functions (mixers, LNAs, VCOs, DACs, ADCs, poweramps, etc.), digital signal processing and computing functions (traditionally done in CMOS), as well asintegrated photonic detectors and possibly transmitters.

The second path in SiGe electronic devices will be to pursue new Si-based material systems that offerthe promise of lattice-matching to Si substrates. The intent here is to remove the stability constraintsthat SiGe device designers currently face, and that limit the useful range of Ge content in practical SiGedevices. The most promising of these new materials is silicon-germanium-carbon (SiGeC). The latticeconstant of C is larger than Si and thus can be used reduce the strain in a SiGe film. Theoretically, itwould only take 1% C to lattice match a 9% Ge film to a Si substrate, 2% C for 18% Ge, etc. Whileresearch is just beginning on the growth of device-quality SiGeC films, and the properties of the resultantfilms has not been firmly established, the SiGeC material system clearly offers exciting possibilities forthe future evolution of SiGe technology. In addition, it has recently been shown that low concentrationsof C can serve to dramatically reduce boron diffusion in conventional SiGe HBTs.52 This has the potentialto allow much more aggressive SiGe HBT profiles to be realized with stable SiGe strained layers. Moreresearch is required to quantify the impact of C on the device electrical characteristics, although initialstudies appear promising.

Acknowledgments

The author would like to thank D.L. Harame, B.S. Meyerson, S. Subbanna, D. Ahlgren, M. Gilbert,K. Ismail, and the members of the SiGe team at IBM Corporation, as well as the past and presentmembers of the Auburn University SiGe research group (A. Joseph, D. Richey, L. Vempati, S. Mathew,J. Roldán, G. Bradford, G. Niu, B. Ansley, K. Shivaram, G. Banerjee, S. Zhang, S. Salmon, and

FIGURE 5.13 Schematic device cross-section of SiGe CMOS technology, consisting of a strained SiGe pFET and astrained Si nFET (after Ref. 51).


U. Gogineni) for their contributions to this work. The support of the Alabama MicroelectronicsScience and Technology Center, ONR, DARPA, NRL, U.S. Army SSDC, Navy NCCOSC, Navy Crane,and MRC are gratefully acknowledged.

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