work in progress --- not for publication draft - not for publication 14 july 2004 – itrs summer...

Work in Progress --- Not for PublicationDRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Interconnect Working GroupInterconnect Working Group

ITRS 2004 Update

14 July 2004

San Francisco


JapanTujimura -sanHideki Shibata

TaiwanDouglas CH Yu

USRobert GeffkenChristopher Case

Europe

Hans Joachim-Barth

Korea

Hyeon-Deok Lee

Hyun Chul Sohn

ITWG Regional Chairs


Agenda• Interconnect scope• Highlight of changes• Difficult challenges

– Review of key issues on materials

• Reliability• Technology requirements issues

– Table updates

• Interconnect performance• Last words


Interconnect scope• Conductors and dielectrics

– Metal 1 through global levels– Starts at pre-metal dielectric (PMD)

• Associated planarization • Necessary etch and surface preparation• Embedded passives• Reliability and system and performance issues• Ends at the top wiring bond pads• Predominantly “needs” based, with some

important exceptions (k and resistivity)


Wire

ViaGlobal (up to 5)

Intermediate (up to 8)

Metal 1

Passivation

Dielectric

Etch Stop Layer

Dielectric Capping Layer

Copper Conductor with Barrier/Nucleation Layer

Pre Metal DielectricTungsten Contact Plug

Metal 1 Pitch

Wire

ViaGlobal (up to 5)

Intermediate (up to 8)

Metal 1

Passivation

Dielectric

Etch Stop Layer

Dielectric Capping Layer

Copper Conductor with Barrier/Nucleation Layer

Pre Metal DielectricTungsten Contact Plug

Metal 1 Pitch

Typical MPU cross section


2004 highlights• Minor changes to low k roadmap

– Color changes only bulk and effective targets remain the same

• Metal one MPU driver matched to overall nodes– Clarification of metal one versus local wiring

• Updated wiring performance metrics– New metrics associated with the increase in Cu resistivity

due to scattering

• Updated Jmax specification• Updated contact resistance• Updated surface preparation metrics


Difficult Challenges• Introduction of new materials to

meet conductivity requirements and reduce the dielectric permittivity*

• Engineering manufacturable interconnect structures compatible with new materials and processes*

• Achieving necessary reliability• Three-dimensional control (3D CD) of

interconnect features (with its associated metrology) is required to achieve necessary circuit performance and reliability.

• Manufacturability and defect management that meet overall cost/performance requirements

• Mitigate impact of size effects in interconnect structures

• Three-dimensional control (3D CD) of interconnect features (with its associated metrology) is required.

• Patterning, cleaning, and filling at nano dimensions

• Integration of new processes and structures, including interconnects for emerging devices

• Identify solutions which address global wiring scaling issues*

<45 nm>45 nm

* Top three grand challenges


• Combinations and interactions of new materials and technologies– interfaces, contamination, adhesion, diffusion, leakage concerns,

CMP damage, resist poisoning, thermal budget, ESH, CoO

• Structural complexity– levels - interconnect, ground planes, decoupling caps– passive elements– mechanical integrity– other SOC interconnect design needs (RF)– cycle time

Engineering manufacturable structures


• Long term – size effects– Microstructural and atom scale effects

• Continued introduction of materials• barriers/nucleation layers for alternate conductors

- optical, low temp, RF, air gap• alternate conductors, cooled conductors

– More reliability challenges

Materials Challenges


• Short term– New failure mechanisms with Cu/low k present

significant challenges before volume production

– Electrical, thermal and mechanical exposure• interface diffusion

• interface delamination

– Higher intrinsic and interface leakage in low k

– Need for new failure detection methodology to establish predictive models

Reliability Challenges


Attaining Dimensional Control• 3D CD of features

– Multiple levels

– performance and reliability implications

– reduced feature size, new materials and pattern dependent processes

• Process problems

– Line edge roughness, trench depth and profile, via shape, etch bias, thinning due to cleaning, CMP effects.

• Process interactions

• CMP and deposition - dishing/erosion - thinning

• Deposition and etch - to pattern multi-layer dielectrics

• Patterning, cleaning and filling at nano dimensions

– particularly DRAM contacts and dual damascene


Technology Requirements • Wiring levels including “optional levels” • Reliability metrics• Minimum wiring/via pitches by level• Performance metric• Planarization requirements• Conductor resistivity• Barrier thickness • Dielectric metrics including effective


MPU HP Near Term Years

New RC delay metric for a 1 mm line (level dependent) –

adjusted for anticipated impact of Cu resistivity rise

YEAR TECHNOLOGY NODE

2003 2004 2005 2006 2007 2008 2009

DRAM ½ PITCH (nm) 100 90 80 70 65 57 50 TECHNOLOGY NODE hp90 hp65 Was

MPU/ASIC ½ PITCH (nm) 107 90 80 70 65 57 50

I s

MPU/ASIC ½ PITCH (nm) 120 107 95 85 76 67 60

Was Number of metal levels 8 9 10 10 10 I s

Number of metal levels 9 10 11 11 11 12 12

Was Local wiring pitch (nm) 245 210 185 170 150 I s

Metal 1 wiring pitch (nm) 240 214 190 170 152 134 120

Was Interconnect RC delay 1 mm line (ps)

176 198 256 303 342

I s

Interconnect RC delay 1 mm line (ps) – intermediate line

191 224 284 335 384 477 595



2003 2004 2005 2006 2007 2008 2009

DRAM ½ PITCH (nm) 100 90 80 70 65 57 50

I s

MPU/ASIC ½ PITCH (nm) 120 107 95 85 76 67 60

I s

Number of metal levels 9 10 11 11 11 12 12

I s

Metal 1 wiring pitch (nm) 240 214 190 170 152 134 120

Was Interlevel metal insulator (minimum expected) —effective dielectric constant ()

3.3–3.6

3.1-3.6

3.1-3.6

3.1-3.6

2.7-3.0

2.7-3.0

2.7-3.0

I s Interlevel metal insulator (minimum expected) —effective dielectric constant ()

3.3–3.6

3.1-3.6

3.1-3.6

3.1-3.6

2.7- 3.0

2.7-3.0

2.7- 3.0

I s Interlevel metal insulator (minimum expected) —bulk dielectric constant ()

<3.0 <2.7 <2.7 <2.7 <2.4 <2.4 <2.4

MPU HP Near Term Years

Cu at all nodes - conformal barriers – resistivity 2.2 -cm


Model for Calculating Copper Wire Resistivity Increase due to Electron-scattering Effect

ρ(W)=ρ0[1+(λ/W)[3/4(1-p)+3/2(r/1-r)]] ρ(W)=ρ0[1+(λ/W)[3/4(1-p)+3/2(r/1-r)]]

ρo=ρ(phonon scattering)+ρ(impurities, vacancies, dislocations) = constant(1.9μΩcm@300K)

λ=MFP(mean free path of charge carriers)=3.4×10-6cm

W=wire width(cm)

ｒ = probability for reflection of electrons at the grain boundaries=0.2

p= portion of electron specularly reflected from the wall=0.5


Cu Wire Resistivity Increase by Electron-scattering Effect

0

1

2

3

4

5

0 100 200 300 400 500Wire width(nm)

Res

isti

vity

(μΩ

cm)

p=0(complete diffuse scattering)

p=0.5

Measured Cu resistivitywithout BM

ρ(Al):2.74μΩcm

p=0.3

Updated(May2004)

From Leti Arnaud-sanresistivity versus linewidth

1,7

1,9

2,1

2,3

2,5

2,7

2,9

3,1

10 100 1000 10000linewidth(nm)

resi

stvi

ty(µ

oh

m.c

m)

calculated with ρo = 1.8 μΩcm,

λ = 40 nm, p= 0.6, r= 0.2

calculated with ρo = 1.8 μΩcm,

λ = 40 nm, p= 0.6, r= 0.2Experimental results shown at IITC 2003 p. 133

New experimental results

MeasuredP=0 P=0.2 P=0.3 P=0.5 data

5.00E-05 1.90E+00 3.40E-06 2.05 2.03 2.02 2.00 2.00E+002.00E-05 1.90E+00 3.40E-06 2.26 2.21 2.19 2.14 2.10E+001.40E-05 1.90E+00 3.40E-06 2.42 2.35 2.32 2.25 2.20E+001.17E-05 1.90E+00 3.40E-06 2.52 2.44 2.40 2.31 2.30E+001.00E-05 1.90E+00 3.40E-06 2.63 2.53 2.48 2.38 2.40E+008.50E-06 1.90E+00 3.40E-06 2.76 2.64 2.58 2.47 2.50E+007.50E-06 1.90E+00 3.40E-06 2.87 2.74 2.68 2.55 2.70E+006.50E-06 1.90E+00 3.40E-06 3.02 2.87 2.79 2.65 2.80E+005.50E-06 1.90E+00 3.40E-06 3.22 3.05 2.96 2.78 3.00E+005.00E-06 1.90E+00 3.40E-06 3.35 3.16 3.06 2.87 Non3.90E-06 1.90E+00 3.40E-06 3.76 3.52 3.39 3.14 Non3.60E-06 1.90E+00 3.40E-06 3.92 3.65 3.52 3.25 Non2.80E-06 1.90E+00 3.40E-06 4.50 4.15 3.98 3.63 Non2.40E-06 1.90E+00 3.40E-06 4.93 4.52 4.32 3.92 Non2.00E-06 1.90E+00 3.40E-06 5.53 5.05 4.81 4.32 Non

ρ (W)(μ Ωcm)wire width(cm) ρ o(μ Ωcm) λ (cm)


ρ and ρeff Calculation Result for Each Wire Level

Metal1 Wiring

IntermediateWiring

Global Wiring

Cu ρ (@300K): ρ 0＝ 1.9 uΩ cmmean free path of charge carriers: λ ＝ 3.40E-06 cm

probability for reflection of electrons at the grain boundaries: r＝ 0.2portion of electron specularly reflected from the wall: p＝ 0.5

year Wiring HalfPitch Trench Height BM thickness BM thickness Cu(w/ o BM） Cu(with BM)of pitch W AR T t_side t_bottom ρ Cu ρ Cu ρ eff

production nm nm nm nm nm uΩ -cm uΩ -cm uΩ-cm2003 240 120 1.6 192 9 9 2.30 2.38 2.932004 214 107 1.7 182 8 8 2.35 2.43 2.992005 190 95 1.7 162 7 7 2.41 2.50 3.062006 170 85 1.7 145 6 6 2.47 2.56 3.112007 152 76 1.7 129 5.4 5.4 2.54 2.64 3.222008 134 67 1.8 121 4.9 4.9 2.62 2.75 3.352009 120 60 1.8 108 4.5 4.5 2.71 2.85 3.502010 108 54 1.8 97 4 4 2.80 2.95 3.622012 84 42 1.8 76 3.2 3.2 3.05 3.26 4.022013 76 38 1.9 72 2.8 2.8 3.18 3.40 4.142015 60 30 1.9 57 2.2 2.2 3.52 3.79 4.622016 54 27 2.0 54 2 2 3.69 4.01 4.882018 42 21 2.0 42 1.6 1.6 4.21 4.62 5.672003 320 160 1.7 272 12 12 2.20 2.26 2.712004 275 138 1.7 234 10 10 2.25 2.31 2.752005 240 120 1.7 204 9 9 2.30 2.38 2.842006 215 108 1.7 183 8 8 2.35 2.43 2.892007 195 98 1.8 176 7 7 2.40 2.48 2.922008 174 87 1.8 157 6 6 2.46 2.55 2.962009 156 78 1.8 140 6 6 2.52 2.63 3.112010 135 68 1.8 122 5 5 2.62 2.74 3.202012 110 55 1.9 105 4 4 2.78 2.93 3.382013 95 48 1.9 90 3.5 3.5 2.92 3.10 3.562015 78 39 1.9 74 3 3 3.14 3.37 3.872016 65 33 2.0 65 2.5 2.5 3.39 3.66 4.172018 55 28 2.0 55 2 2 3.66 3.96 4.452003 475 238 2.1 499 12 12 2.10 2.13 2.422004 410 205 2.1 431 10 10 2.14 2.16 2.452005 360 180 2.2 396 9 9 2.17 2.20 2.502006 320 160 2.2 352 8 8 2.20 2.24 2.542007 290 145 2.2 319 7 7 2.23 2.27 2.572008 260 130 2.3 299 6 6 2.27 2.31 2.602009 234 117 2.3 269 6 6 2.31 2.36 2.692010 205 103 2.3 236 5 5 2.37 2.42 2.742011 165 83 2.3 190 4 4 2.49 2.55 2.892012 140 70 2.4 168 3.5 3.5 2.59 2.67 3.032013 117 59 2.4 140 3 3 2.73 2.82 3.212014 100 50 2.5 125 2.5 2.5 2.87 2.98 3.372015 83 42 2.5 104 2 2 3.07 3.19 3.60


Cu ρ (@300K): ρ 0＝ 1.9 uΩ cmmean free path of charge carriers: λ ＝ 3.40E- 06 cm

probability for reflection of electrons at the grain boundaries: r＝ 0.2portion of electron specularly reflected from the wall: p＝ 0.5

year Wiring HalfPitch Trench Height BM thickness BM thickness Cu(w/ o BM） Cu(with BM)of pitch W AR T t_side t_bottom ρ Cu ρ Cu ρ eff

production nm nm nm nm nm uΩ - cm uΩ - cm uΩ - cm2003 240 120 1.6 192 9 9 2.30 2.38 2.932004 214 107 1.7 182 8 8 2.35 2.43 2.992005 190 95 1.7 162 7 7 2.41 2.50 3.062006 170 85 1.7 145 6 6 2.47 2.56 3.112007 152 76 1.7 129 5.4 5.4 2.54 2.64 3.222008 134 67 1.8 121 4.9 4.9 2.62 2.75 3.352009 120 60 1.8 108 4.5 4.5 2.71 2.85 3.502010 108 54 1.8 97 4 4 2.80 2.95 3.622011 94 47 1.8 85 3.5 3.5 2.93 3.11 3.812012 84 42 1.8 76 3.2 3.2 3.05 3.26 4.022013 76 38 1.9 72 2.8 2.8 3.18 3.40 4.142014 68 34 1.9 65 2.5 2.5 3.33 3.57 4.352015 60 30 1.9 57 2.2 2.2 3.52 3.79 4.622016 54 27 2.0 54 2 2 3.69 4.01 4.882017 48 24 2.0 48 1.8 1.8 3.92 4.28 5.232018 42 21 2.0 42 1.6 1.6 4.21 4.62 5.67

ρ and ρeff Calculation Result for M1 Wire Levelfor Every Year


Wire width < mean free path of electrons

↓Surface scattering dominantp=0 (complete diffuse scattering)

p=1 (specular scattering)

↓Resistivity increases

even if the barrier metalIs 0 thickness

↓barrier/Cu interface smoothing

might be a solution

p: fraction of electrons having elastic collisions at wire surfaces

0

1

2

3

4

5

0 0.1 0.2 0.3 0.4 0.5

Line width (nm)

Res

isti

vity

(μΩ

cm) p=0

p=0.5

Measured Cu resistivitywithout barrier material

Cu resistivity increase


Currently introduced in volume production – behind schedule

Keff = 3.1 could be achieved by integration of dense 2.7- type material with SiC-based assist layer at k=4.5

Keff = 2.7 cannot be achieved by • integration of a dense 2.7- type material with SiC-based assist layers at k=4.5• or a porous 2.4 material if sidewall etch damage occurs even without etch-stop

Introduction of lower k hardmask and etch-stop

layers required to achieve keff

Significant innovation required in the areas of• Damage-free etch, ash and clean• Damage-free integration• Low k materials

Keff = 2.5 will require:• Bulk low k of <2.2 with minimal sidewall damage• low k hardmask and etch- stop layers (k<2.8)• Elimination of trench etch- stop desirable

Introduction of metal cap and low k diffusion

barrier/vias etch-stop

Year of Production 2003 2004 2005 2006 2007 2008 2009 2010 2012 2013 2015 2016 2018Technology Node hp90 hp65 hp45 hp32 hp22MPU/ASIC ½ Pitch (nm) 120 107 95 85 76 67 60 54 42 38 30 27 21Interlevel metal insulator (minimum expected) – bulk dielectric constant (k)

<3.0 <2.7 <2.7 <2.7 <2.4 <2.4 <2.4 <2.1 <2.1 <1.9 <1.9 <1.7 <1.7

Interlevel metal insulator (minimum expected) – effective dielectric constant (k)

3.3– 3.6 3.1–3.6 3.1–3.6 3.1–3.6 2.7–3.0 2.7–3.0 2.7–3.0 2.3-2.6 2.3-2.6 2.0-2.4 2.0-2.4 <2.0 <2.0

k effective roadmap discussion



2012 2015 2018

DRAM ½ PITCH (nm) 35 25 18

MPU/ASIC ½ PITCH (nm) 42 30 21

MPU PRINTED GATE LENGTH (nm) 25 18 13

MPU PHYSICAL GATE LENGTH (nm) 18 13 9.0

Number of metal levels 12 13 14 Total interconnect length (m/cm2) – active wiring only, excluding global levels (footnote for calculation)

2214 3544 5035

Metal 1 wiring pitch (nm) 84 60 42 Metal 1 A/R (for Cu) 1.8 1.9 2.0 Intermediate wiring pitch (nm) 110 78 55 Intermediate wiring dual damascene A/R (Cu wire/via) 1.9/1.7 1.9/1.7 2.0/1.8 Minimum global wiring pitch (nm) 165 117 83 Global wiring dual damascene A/R (Cu wire/via) 2.3/2.1 2.4/2.2 2.5/2.3 Cu thinning global wiring due to dishing (nm), 100 micron wide feature

13 9 7

Conductor effective resistivity (-cm) Cu intermediate wiring*

2.2 2.2 2.2

Barrier/cladding thickness (for Cu intermediate wiring) (nm)***

4 3 2

Interlevel metal insulator—effective dielectric constant () 2.3-2.6 2.0-2.4 <2.0

Interlevel metal insulator (minimum expected) —bulk dielectric constant ()

<2.1 1.9 <1.7

MPU HP Long Term Years

Conductor effective resistivity (red) because of scattering effects -

research requiredAtomic dimension barriers – zero thickness barrier desirable but not required


Updated Jmax Table (Near-term)

Table 81a MPU Interconnect Technology Requirements—Near-term

Year of Production 2003 2004 2005 2006 2007 2008 2009

Technology Node hp90 hp65

WAS DRAM ½ Pitch (nm) 100 90 80 70 65 57 50

IS

WAS MPU/ASIC ½ Pitch (nm) 120 107 95 85 76 67 60

IS

WAS MPU Printed Gate Length (nm) 65 53 45 40 35 32 28

IS

WAS MPU Physical Gate Length (nm) 45 37 32 28 25 22 20

IS

WAS Number of metal levels 9 10 11 11 11 12 12

IS

WASNumber of optional levels – ground planes/capacitors

4 4 4 4 4 4 4

IS

WASTotal interconnect length (m/cm2) – active wiring only, excluding global levels [1]

579 688 907 1002 1117 1401 1559

IS

WAS FITs/m length/cm2 10-3 excluding global levels [2]

8.6 7.3 5.5 5 4.5 3.6 3.3

IS

WAS Jmax (A/cm2) – intermediate wire (at 105C)

3.70E+05 5.00E+05 6.80E+05

7.80E+05 1.00E+06 1.40E+06 2.50E+06

IS 3.36E+05 5.25E+056.83E+0

59.34E+05 1.39E+06 1.59E+06 1.86E+06


ITRS2003 eff Roadmap Revision

1.5

2.0

2.5

3.0

3.5

4.0

Eff

ecti

ve D

iele

ctri

c C

onst

ant;

ef

f4.5

070605040302 08

Year of 1st Shipment (=ES)

Red Brick Wall(Solutions are NOT known)

Solutions areknown

Solutions existor

being optimized

1312111009 14

Calculated based on delay time using typical critical path

Estimated by typical low-materials and ILD structures=3.0-3.3

=2.0-2.4

<1.7

Described in roadmap tableat ITRS2002

=2.4-2.8

=2.6-3.0


Modulus vs k-value

Low-k materials from Applied Materials, ASM, Dow Chemical, Honeywell, JSR, Novellus

0

2

4

6

8

10

12

1.822.22.42.7

k-value

Str

eng

th (

Mo

du

lus

GP

a)

Eas

e o

f In

teg

rati

on

Soft Pine

HardRubber

Wax

90

nm

65

nm

45

nm

0

2

4

6

8

10

12

1.822.22.42.7

k-value

Str

eng

th (

Mo

du

lus

GP

a)

Eas

e o

f In

teg

rati

on

Soft Pine

HardRubber

Wax

90

nm

65

nm

45

nm


Technology Requirements Near Term:Technology Requirements Near Term:Modifications of Low-k Material and CD Metrics Modifications of Low-k Material and CD Metrics

Dielectric Constant Delta: Take into Account Total Clean ProcessDielectric Constant Delta: Take into Account Total Clean ProcessAdd Profile Change as MetricAdd Profile Change as Metric

Table 83a Interconnect Surface Preparation Technology Requirements*—Near-term Rick and SkipYear of Production 2003 2004 2005 2006 2007 2008 2009 Driver


DRAM ½ Pitch (nm) 100 90 80 70 65 57 50 D ½

MPU / ASIC ½ Pitch (nm) 107 90 80 70 65 57 50 M

MPU Printed Gate Length (nm) 65 53 45 40 35 32 28 M

MPU Physical Gate Length (nm) 45 37 32 28 25 22 20 M

Wafer diameter (mm) 300 300 300 300 300 300 300 D ½, M

Wafer edge exclusion (mm) 2 2 2 2 2 2 2 D ½, M

Was Maximum Dielectric Constant Increase due to Strip + Clean [L] 4.00% 2.50% 2.50% 2.50% 2.50% 2.50% 2.50% M

Was Maximum Dielectric Constant Increase Due to Rework [L] 4.00% 2.50% 2.50% 2.50% 2.50% 2.50% 2.50% M

I s Maximum Dielectric Constant Increase Due to Rework, Strip + Clean [L] 4.00% 2.50% 2.50% 2.50% 2.50% 2.50% 2.50% M

Maximum Effect on Dielectric Critical Dimenstion due to Strip + Clean [M]

2.50% 2.50% 2.50% 2.50% 2.50% 2.50% 2.50% M

Add Maximum Allowable Bow Due to Strip + Clean (nm) [N] 15 15 15 15 10 10 10 M

Cleaning Effects on Dielectric Material


Technology Requirements Near Term:Technology Requirements Near Term:Post-CMP Cleaning Metrics Post-CMP Cleaning Metrics

New Format Proposed with Focus on Post-CMP CleanNew Format Proposed with Focus on Post-CMP CleanWatermarks and Surface Roughness of Cu IncludedWatermarks and Surface Roughness of Cu Included

I s Table 83c Post CMP Clean Technology Requirements*—Near-termYear of Production 2003 2004 2005 2006 2007 2008 2009 Driver


DRAM ½ Pitch (nm) 100 90 80 70 65 57 50 D ½

MPU / ASIC ½ Pitch (nm) 107 90 80 70 65 57 50 M

MPU Printed Gate Length (nm) 65 53 45 40 35 32 28 M

MPU Physical Gate Length (nm) 45 37 32 28 25 22 20 M

Wafer diameter (mm) 300 300 300 300 300 300 300 D ½, M

Wafer edge exclusion (mm) 2 2 2 2 2 2 2 D ½, M

Killer Defect Density, DpRp (#/cm2) [A] 0.0172 0.0217 0.0283 0.0185 0.0233 0.0185 0.0199 D ½

Critical Particle Diameter, dc (nm) [B] 50 45 40 35 32.5 27.5 25 D ½

Critical Particle Density, Dpw (#/wafer) [C] 59 75 97 64 80 54 68 D ½

AddAdd Critical Defect Diameter,dc (nm) [D] 50.0 45.0 40.0 35.0 32.5 27.5 25.0 M

AddAdd Maximum RMS (nm) 1.5 1.5 1.5 1.5 1.0 1.0 1.0 M

Critical front surface metals (109 atoms/cm2) (H) 50 50 10 10 10 10 10 M

Critical back surface metals (Cu) (109 atoms/cm2) (I) 1000 1000 1000 1000 500 500 500 M

Mobile ions (1010 atoms/cm2) [J] 5 5 5 5 2.5 2.5 2.5 D ½

Organic contamination (1013 C at/cm2) [K] 1.8 1.6 1.4 1.3 1.2 1.0 0.9 M

Watermarks

Front surface particles

Metallic Contamination

Surface Roughness


• Cross TWG work from FEP

• Technology requirements address:– Killer defect density and size– Back surface particles– Metallic and organic contamination– Dielectric constant change (increase) due

to stripping, cleaning and rework

Surface preparation


Cross TWG Issues• Metrology

– Discussion on need for in-line texture measurements – no– Need owner for precision gas and liquid flow specifications for new processes such as

ALD– Possible need for in-line etch depth monitoring for etch-stop free dual damascene

• Factory Integration– Discussed trends in some 300 mm processes which show dramatic rise in gas

consumption that are not scaling from 200 mm• Yield - Long list of addressable issues related to contamination and purity of fluids and

precursors, slurry characterization

• ESH – Clarification of dilute Cu waste stream reclaim/recovery– Plan to introduce new metrics related to precursor (or other material) utilization efficiency– Need to identify chamber cleaning gases (which are increasing rapidly for 300 mm single

wafer) for reduction– Begin 2005 task to renew table of hazardous materials

• A&P– Interconnect will provide mechanical properties of dielectric stack

• Test – concerns over mechanical damage to weaker dielectrics from probing


2005 Thoughts

• Metal 1 design rule concerns– Resolved confusion over non -contacted versus contacted

half-pitch and the incorrect use of technology node for MPU– Recent publications suggest M1 scaling may be accelerating– Desirable to have separate tables for high performance

• High performance MPU pitches scaling at ~0.7/3 years• High performance ASIC pitches scaling at ~0.75-0.8/ 2

years• Decoupled from DRAM at 0.7/3 years

• Dialog started with Design, A&P and Test to identify directions for 3D ICs – may address global wiring problem


Global Interconnect

Design and Signaling OptionsPackage Intermediated Interconnect3D InterconnectsRF/Microwave InterconnectsOptical InterconnectsRadical solutions spin nanotubes molecular superconductors other

2003 2005 2007 2009 2011

Research

Narrow Options

Implementation

Global interconnect roadmap


Last words• Continued changes in materials• Develop solutions for emerging devices• Must manage 3D CD • System level solutions must be accelerated to

address the global wiring grand challenge – Cu resistivity increase impact appears ~2006– materials solutions alone cannot deliver

performance - end of traditional scaling – integrated approach with design and packaging

work in progress --- not for publication draft - not for publication 14 july 2004 – itrs summer...

Documents

publication draft

group itrs

resistivity slide

performance issues

san francisco slide

d cd of interconnect

interactions of new

associated metrology