tables focus b itrs

2009 LINKS AND TABLE LISTTABLE LINKS

Emerging Research Devices

Emerging Research Materials

ORTC TablesFOCUS A TablesFOCUS B TablesFOCUS C TablesFOCUS D TablesFOCUS E TablesFOCUS F TablesCROSS CUT A TablesCROSS CUT B Tables2009 ITRS Table Listing2009 ITRS Chapter Page

Table ERD1Table ERD2Table ERD3Table ERD4Table ERD5Table ERD6Table ERD7aTable ERD7bTable ERD7c

Table ERD8Table ERD9Table ERD10Table ERD11Table ERD12Table ERD13Table ERD14Table ERD15

Table ERM1Table ERM2Table ERM3Table ERM4Table ERM5Table ERM6Table ERM7Table ERM8Table ERM9Table ERM10Table ERM11Table ERM12

http://www.itrs.net/Links/2009ITRS/Home2009.htm

Overall Technology Roadmap Characters. (Key Roadmap Drivers)Test & Test Equipment | RF and AMS for WirelessEmerging Research Devices (ERD) | Emerging Research Materials (ERM)Front-end Processes (FEP) | Process Integration, Devices, & Structures (PIDS)Lithography | Factory IntegrationInterconnect | Assembly and PackagingSystem Drivers | Design Environment, Safety, & Health (ESH) | Metrology | Modeling & SimulationYield Enhancement 2009 ITRS tables and titles list2009 ITRS page of reports online

Emerging Research DevicesEmerging Research Devices Difficult ChallengesMemory TaxonomyCurrent Baseline and Prototypical Memory TechnologiesTransition Table for Emerging Research Memory DevicesEmerging Research Resistance-based Memory Devices—Demonstrated and Projected ParametersTransition Table for Emerging Research Logic DevicesMOSFETS:Extending the channel to the End of the RoadmapCharge based Beyond CMOS: Non-Conventional FETs and other Charge-based information carrier devicesAlternative Information Processing Devices

Prototypical criteria for emerging device architecturesSummary of the attributes of several emerging research devices and projections for their application spaces.Challenges in Existing Memory SystemsOpportunities for Emerging Memory DevicesHardware requirements for the three basic approaches to probabilistic inferencePotential Evaluation for Emerging Research Memory DevicesPotential Evaluation for Emerging Research Logic and Alternate Information Processsing Devices

Emerging Research MaterialsEmerging Research Material Technologies Difficult ChallengesApplications of Emerging Research MaterialsChallenges for ERM in Alternate Channel ApplicationsAlternate Channel Material Properties -- Protected Sheet NEED PASSWORDSpin Material PropertiesERM Memory Material ChallengesChallenges for Lithography MaterialsFEP / PIDS Challenges for Self AssemblyInterconnect Material ChallengesNanomaterial Interconnect Material PropertiesAssemby & Package ERM ChallengesITWG Earliest Potential ERM Insertion Opportunity Matrix

Research and Technology Development Schedule proposed for Carbon-based Nanoelectronics to impact the Industry's Timetable for Scaling Information Processing Technologies.

Table ERD1 Emerging Research Devices Difficult Challenges

The International Technology Roadmap for Semiconductors, 2009 Edition

Summary of Issues and opportunities

Invent and develop a new information processing technology eventually to replace CMOS

Bridge a knowledge gap that exists between materials behaviors and device functions.

Accommodate the heterogeneous integration of dissimilar materials

Reliability issues should be identified & addressed early in the technology development

Difficult Challenges ³ 16 nm and < 16 nm

Scale high-speed, dense, embeddable, volatile and non-volatile memory technologies to and beyond the 16 nm technology generation.

SRAM and FLASH scaling will reach definite limits within the next several years (see PIDS Difficult Challenges). These are driving the need for new memory technologies to replace SRAM and FLASH memories.

Identify the most promising technical approach(es) to obtain electrically accessible, high-speed, high-density, low-power, (preferably) embeddable volatile and non-volatile RAM

The desired material/device properties must be maintained through and after high temperature and corrosive chemical processingReliability issues should be identified & addressed early in the technology development

Scale CMOS to and beyond the 16 nm technology generation.Develop new materials to replace silicon as an alternate channel and source/drain to increase the saturation velocity and maximum drain current in MOSFETs while minimizing leakage currents and power dissipation for technology scaled to 16 nm and beyond.

Develop means to control the variability of critical dimensions and statistical distributions (e.g., gate length, channel thickness, S/D doping concentrations, etc.)

Accommodate the heterogeneous integration of dissimilar materialsThe desired material/device properties must be maintained through and after high temperature and corrosive chemical processingReliability issues should be identified & addressed early in t

Extend ultimately scaled CMOS as a platform technology into new domains of application.

Discover and reduce to practice new device technologies and a primitive-level architecture to provide special purpose optimized functional cores heterogeneously integrable with silicon CMOS.

Continue functional scaling of information processing technology substantially beyond that attainable by ultimately scaled CMOS.

Ensure that a new information processing technology is compatible with the new memory technology discussed above; i.e., the logic technology must also provide the access function in a new memory technology.

The desired material/device properties must be maintained through and after high temperature and corrosive chemical processing

Table ERD2 Memory Taxonomy


Cell Element Type Non-volatility Retention Time

1T1R or 1D1R [A]

MRAM Nonvolatile > 10 yearsPhase change memory Nonvolatile > 10 years

Macromolecular memory Nonvolatile > yearsMolecular memory Nonvolatile > years

Nonvolatile > years

Nanothermal Nonvolatile > yearsNanoionic memory Nonvolatile > years

Electronic effects memory Nonvolatile > years

1T1C [A]DRAM Volatile ~ seconds

FeRAM [B] Nonvolatile > 10 years

1T [A]

FB DRAM [A] Volatile < secondsFloating gate memory Nonvolatile > 10 years

SONOS Nonvolatile > 10 yearsFeFET memory [A] Nonvolatile > years

Multiple T [A]SRAM Volatile large

STTM [C] Volatile small

Notes for Table ERD2:

[B] FeRAM—ferroelectric RAM with one ferroelectric transistor and one ferroelectric capacitor

Nano-electro-mechanical memory

[A] 1T1R—1 transistor–1 resistor 1D1R—1 diode–1 resistor 1T1C—1 transistor–1 capacitor 1T—1 transistor FB DRAM—floating body DRAM FeFET—ferroelectric FET Multiple T—multiple transistor

[C] STTM—scaleable 2-transistor memory. J. H. Yi, W. S. Kim, S. Song, Y. Khang, H.-J. Kim, J. H. Choi, H. H. Lim, N. I. Lee, K. Fujihara, H.-K. Kang, J. T. Moon, and M. Y. Lee. “Scalable Two-transistor Memory (STTM).” IEDM 2001 p. 36.1.1–4.

Table ERD3 Current Baseline and Prototypical Memory Technologies


Baseline Technologies Prototypical Technologies [A]DRAM

SRAM [C]Floating Gate [E]

FeRAM MRAM PCMStand-alone [A]

EmbeddedNOR NAND

[C]

Storage Mechanism Charge on a capacitor Charge on floating gate

Cell Elements 1T1C 6T 1T 1T 1T1C 1(2)T1R 1T1R

2009 50 65 65 90 90 50 180 130 65

2024 8 20 10 18 18 10 65 16 8

Cell Area20092024

Read Time20092024 70 ps

W/E Time

2009 1/0.1 ms 50/120ns[P]10 ms

2024 70 ps1 ms/

10 ms 0.1 ms

2009 64 ms 64 ms [D] >10 y > 10 y >10 y >10 y >10 y >10 y

2024 64 ms [D] >10 y > 10 y >10 y >10 y >10 y >10 y

Write Cycles2009 >1E16 >1E16 >1E16 >1E5 >1E5 1.00E+05 1.00E+14 >1E16 1.00E+09

2024 >3E16 >3E16 >3E16 >1E5 >1E5 1.00E+06 >1E16 >1E16 1.00E+15

2009 2.5 2.5 1 12 15 7–9 0.9-3.3 1.5 [M] 3 [P]

2024 1.5 1.5 0.7 12 15 4-6 0.7–1 <1.5 <3

2009 1.8 1.8 1 2 2 1.6 0.9–3.3 1.5 [M] 3

2024 1.5 1.5 0.7 1 1 1 0.7–1 <1.8 <3

2009 5E-15 [B] 5.00E-15 7.00E-16 >1E-14 [F]>1E-14

1E-13 [H] 3E-14 [L] 1.5E-10 [A] 6E-12 [Q][F]

2024 2E-15 [B] 2.00E-15 2.00E-17>1E-15 >1E-15

>1E-15 7E-15 [L] 1.5E-13 [A] <2E-13 [Q][F] [F]

Comments

Trapping Charge [G]

Inter-locked state of logic

gates

Charge trapped in

gate insulator

Remnant polarization

on a ferroelectric

capacitor

Magnetization of ferromagnetic layer

Reversibly changing

amorphous and

crystalline phases

Feature size F, nm

6F2 (12-30)F2 140 F2 10 F2 5 F2 (6-7)F2 22F2 45F2 16F2

4F2 (12-30)F2 140 F2 10 F2 5 F2 (9-10)F2 12F2 10F2 6F2

<10 ns 1 ns 0.3 ns 10 ns 50 ns 14 ns 45 ns [I] 20 ns [M] 60 ns [P]

<10 ns 0.2 ns 1.5 ns 8 ns 2.5 ns <20 ns [J] <0.5 ns < 60 ns

<10 ns 0.5 ns 0.3 ns1 ms/

20ms/20ms[H] 10 ns [K] 20 ns [M]

<10 ns 0.15 ns1 ms/

~10ms/10ms 1 ns[J] <0.5 ns [N] <50 ns

Retention Time 64 ms

Write Operating Voltage (V)Read Operating Voltage (V)

Write Energy (J/bit)

Multiple-bit potential



Destructive read-out

Spin-polarized Write has a potential to lower write

current density and energy

[O],


Table ERD3 Current Baseline and Prototypical Memory Technologies


Notes for Table ERD3:

[A] 2009 ITRS PIDS chapter.

[C] See the Embedded Memory Requirements table in the System Drivers chapter.

[D] SRAM memory state is preserved so long as voltage is applied.

[E] Embedded applications (see the Embedded Memory Requirements table in the System Drivers chapter).

[F] Lower bound for Fowler Nordheim write/erase.

[G] Trapping charge memories in PIDS chapter include SONOS, and a number of engineered barrier concepts, some of which are described in Table ERD5a.

[H] J-Y. Wu et al. “A Single-Sided PHINES SONOS Memory Featuring High-Speed And Low-Power Applications.” IEEE Electr. Dev. Lett. 27 (2006) 127.

[K] H. Kohlstedt et al. “Current Status And Challenges Of Ferroelectric Memory Devices.” Microelectronic Eng. 80 (2005) 296-304.

[M] N. Sakimura et. al. “MRAM Cell Technology For Over 500-MHz SOC.” IEEE J. Solid-State Circ. 42 (2007) 830-838.

[N] H. W. Schumacher. “Ballistic bit addressing in a magnetic memory cell array.” Appl. Phys. Lett. v. 87 , no. 4 (2005) 42504.

[B] Estimated as E~0.5*CV2 for C=25fF, Vc=0.60 Volts (in 2009) and Vc=0.35 Volts in 2024 (energy to refresh is not included).

[I] K. R. Udayakumar et al. “Full-Bit Functional, High-Density 8 Mbit One Transistor-One Capacitor Ferroelectric Random Access Memory Embedded Within A Low-Power 130 nm Logic Process.” Jap. J. Appl. Phys. 46 (2007) 2180-2183.

[J] “Nanoelectronics and Information Technology.” Ed. Rainer Waser. Wiley-VCH, 2003, 568-569.

[L] Estimated as E~0.5*q*A*V for q=13.5 mC/cm2, A=0.33mm2, Vc=1.5 Volts (in 2009) and q=30 mC/cm2, A=0.069mm2, Vc=0.7 Volts (in 2024).

[O] Y. Jiang, T. Nozaki, S. Abe, T. Ochiai, A. Hirohata, N. Tezuka, K. Inomata. “Substantial Reduction Of Critical Current For Magnetization Switching In An Exchange-Biased Spin Valve.” Nature Materials, v. 3, June 2004, 361-364.

[P] W. Y. Cho, B-H Cho, B-G. Choi, H-R Oh, S. Kang, K-S. Kim, K-H. Kim, D-E. Kim, C-K. Kwak, H-G. Byun, Y. Hwang, S. J. Ahn, G-H. Koh, G. Jeong. H. Jeong, and K. Kim.“A 0.18-mm 3.0-V 64-Mb Nonvolatile Phase-Transition Random Access Memory (PRAM).” IEEE J

[Q] Estimated as E~0.5*I2R*tw for I=202 mA, R=6 kOhm, tw=50 ns (in 2009) and I=12mA, R=45 kOhm, <50 ns (in 2024).

Table ERD4 Transition Table for Emerging Research Memory Devices


IN/OUT (Table ERD5) Reason for IN/OUT Comment

Engineered tunnel barrier memory OUT

Natural evolution of FG FLASH

Became a prototypical technology

Nanothermal memory IN

Nanoionic memory IN Replacement for the Ionic memory

Spin Torque Transfer MRAM IN

ERD recommends to cover engennered tunnel barrier memory in PIDS as part of FG.

Band-gap engineered SONOS is already included in PIDS chapter since 2007

Replacement for the Fuse/Antifuse Memory

Device types: 1) Fuse/Antifuse Memory, 2) Nanowire PCM

Advanced version of MRAM with better scaling potential

Table ERD5 Emerging Research Resistance-based Memory Devices—Demonstrated and Projected Parameters


Capacitance-Resistance-based

based

Nanoionic MemoryMacromolecular

Molecular MemoriesMemory

Storage Mechanism

Ion transport and

Multiple mechanisms Multiple mechanisms Multiple mechanisms

redox reaction

Cell Elements 1T 1T1R or 1D1R 1T1R 1T1R or 1D1R 1T1R or 1D1R 1T1R or 1D1R 1T1R or 1D1R 1T1R or 1D1R

Device Types

1) cation migration 1) Charge trapping

M-I-M (nc)-I-M Bi-stable switch2) telescoping CNT 2) nanowire PCM 2) anion migration 2) Mott transition

3) Nanoparticle 3) FE barrier effects

Feature size F

Min. required

Best projected

Demonstrated

Cell Area

Min. required

Best projected

Demonstrated Data not available Data not available Data not available Data not available Data not available Data not available

Read Time

Min. required

Best projected

Demonstrated ~40ns[C3] Data not available Data not available Data not available

W/E time

Min. required

Best projected

Demonstrated 2ns [C4] 5 ns/5 ns [E3,E4] 0.2 s [H3]

Retention Time

Min. required >10 y >10 y >10 y >10 y >10 y >10 y >10 y

Best projected >10 y >10 y >10 y >10 y >10 y Not known Not known

Demonstrated ~days [B1] >10 y[C1] >8 months [D1] >10 y [E5] 1 y [F3] 6 month [G4] 2 months [H4]

Write Cycles

Min. required >1E5 >1E5 >1E5 >1E5 >1E5 >1E5 >1E5 >1E5

Best projected >1E16 >1E16 >1E16 >1E16 >1E16 >1E16 >1E16 >1E16

Demonstrated 1.00E+12 >1E9 [B1] >1E12 [C4] >1E6 [D1] >1E9 [E6] >1E3 [F4] >1E6 [G2] >2E3 [H2]

Min. required

Best projected Not known [B4] <1 V 0.5/1 <0.5 V [E7] <3 V <1 V [G1] 80 mV[H5]

Demonstrated 1.5 V [B1] 0.5/1 [D1] 0.6/-0.2 [E1] 3-5 V [F1,F2]

Min. required 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5

Best projected 0.7 0.7 <0.5 <0.5 <0.2 V [E7] 0.7 0.7 0.3 [H1]

Demonstrated 2.5 [A4] 1.5 V [B1] 0.7 [C3] 0.4 [D1] 0.15 V[E1] 0.7 V [F1] 1 V [G2] 0.5 V [H2]

Write energy (J/bit)

Min. required

Best projected 2E-15 [A6] Not known [B4] <1E-13 Not known 1E-15 [E8] <1E-10 Not known 2E-19 [H6]

Demonstrated Data not available Data not available 4E-12 [C4] 1E-12 [D4] 5E-14 [E9] 1E- 9 [F5] 1E-13 [G3] Data not available

Comments

Research activity [I1] 55 19 36 99 158 77 103 63

Ferroelectric FET memory

Nanomechanical Memory

Spin Torque Ttransfer Memory

Nanothermal Memory

Electronic Effects Memory

Remnant polarization on a ferroelectric gate

dielectric

Electrostatically-controlled

mechanical switch

Magnetization of the ferromagnetic layer

Thermo-chemical redox process, 2) Thremal phase transformations

FET with FE gate insulator

1) nanobridge/ cantilever

Magnetization change by spin transfer torque

1) Fuse/Antifuse Memory

<65 nm <65 nm <65 nm <65 nm <65 nm <65 nm <65 nm <65 nm

22 nm [A1] 5-10 nm [B1] 7-10 nm 5-10 nm 5-10 nm 5-10 nm 5-10 nm 5 nm [H1]

~2 mm [A2] 180 nm [B2] 50 nm [C1] 180 nm [D1] 90 nm [E1] 1 mm [F1] 250 nm [G1] 30 nm [H2]

8F2/4F2 [A3] 10F2 10 F2 10 F2 10 F2 10 F2 10 F2 10 F2

8F2/4F2 [A3] 5F2 6F2 [C2] 8/5F2 [D2] 8/5F2 [D2] 8/5F2 [D2] 8/5F2 [D2] 5F2

16F2 [C3] 8F2 [E1]

<15 ns <15 ns <15 ns <15 ns <15 ns <15 ns <15 ns <15 ns

2.5 ns <3 ns <10 ns <10 ns <10 ns <10 ns <10 ns <10 ns [H1]

20 ns [A4] 3 ns [B3] <50 ns [E1] ~10 ns [G2]

Application dependent








2.5 ns [A1] <1 ns [B1,B2] <2 ns <10 ns <20 ns [E2] <20 ns [F2] <10 ns <40 ns [H1]

20 ns [A5] 3 ns [B3] 10 ns/5 ns [D3] 100 ns [F2] 10 ns [G2]

>10 y

>10 y [A5]

>30 days [A5]

Write operating voltage (V)









<0.9 V [A1]

±4[A5] ~±1.0 [C4] ~±2 [G2] ~±1.5 V [H2]

Read operating voltage (V)









Potential for non-destructive readout

Inverse voltage scaling presents a problem

Potential for multi-bit storage Prototype chips demo at leading tech [C3]

Perpendicular TMR [C1]

Potential for multi-bit storage

2 Mbit prototype chip demonstrated [E1]


160 Kbit prototype chip demonstrated [H3]


Low read voltage presents a problem

Low read voltage presents a problem



CNT—carbon nanotube

Notes for Table ERD5b:

[A1] Fitsilis M, Mustafa Y, Waser R, Scaling the ferroelectric field effect transistor, INTEGRATED FERROELECTRICS 70: 29-44 2005

[A4] H. Ishiwara, “Application of Bismuth-layered perovskite thin films to FET-type ferroelectric memories”, Integrated Ferroelectrics 79 (2006) 3-13

[A5] H. Ishiwara, "Current status of ferroelectric-gate Si transistors and challenge to ferroelectric-gate CNT transistors", Curr. Appl. Phys. 9 (2009) S2-S6

[A6] Calculated based on the parameters of scaled FE capacitor projected in Ref. [A1]

[B1] T. Rueckes et al. “Carbon nanotube-Based Nonvolatile Random Access Memory for Molecular Computing.” Science 289 (2000): 94-97.

[B3] www.nantero.com

[D2] 8F2 for 1T1R, 5F2 for 1R cells.

[D3] K. Tsunoda, et al. "Low power and high speed switching of Ti-doped NiO ReRAM under the unipolar voltage source of less than 3V", IEDM 2007, 767-770

[D4] Estimated based on experimental data reported in Ref. [D1]: E~0.5*V*I*tw , for V=1 Volt, I=0.5mA , tw=10 ns

[A2] M. Takashashi and S. Sakai, “Self-aligned-gate Metal/Ferroelectric/Insulator/Semiconductor field-effect transistors with long memory retention”, Jap. J. Appl. Phys. 44 (2005) L800-L802

[A3] 4F2 is for NAND or multiple bit storage, see e.g. Y Tabuchi, S. Hasegawa, T. Tamura, H. Hoko, K. Kato, Y. Arimoto, H. Ishiwara, “Multi-bit programming for 1T-FeRAM by local polarization method”, 2005 SSDM, pp. 1038-1039

[B2] J. W. Ward, M. Meinhold, B. M. Segal, J. Berg, R. Sen, R. Sivarajan, D. K. Brock, and T. Rueckes. “A Non-Volatile Nanoelectromechanical Memory Element Utilizing A Fabric Of Carbon Nanotubes.” Non-Volatile Memory Technology Symposium, 15-17 Nov. 2004,

[B4] The projections for WRITE voltage and WRITE energy depend on the length of nanoelectromechanical element. For very small length, the operating voltage might be too high for practical use, as follows from theoretical analysis in: M. Dequesnes et al. “

[C1] T. Kishi, et al. "Lower-current and Fast switching of A Perpendicular TMR for High Speed and High density Spin-Transfer-Torque MRAM" Electron Devices Meeting, 2008. IEDM 2008. IEEE International (2008).

[C2] U.K. Klostermann, et al. "A Perpendicular Spin Torque Switching based MRAM for the 28 nm Technology Node" Electron Devices Meeting, 2007. IEDM 2007. IEEE International (2007).

[C3] T. Kawahara, et al. "2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read" 2007 ISSCC Technical Digest, 480 (2007).

[C4] M. Hosomi, et al. "A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching:Spin-RAM" 2005 IEDM Technical Digest, 459 (2005).

[D1] G. Baek, et al. "Highly Scalable Nonvolatile Resistive Memory Using Simple Binary Oxide Driven By Asymmetric Unipolar Voltage Pulses.” 2004 International Electron Devices Meeting, San Francisco, CA, USA, 13/12/2004-15/12/2004, 587-90.

[E1] S. Dietrich, M. Angerbauer, M. Ivanov, D. Gogl, H. Hoenigschmid, M. Kund, C. Liaw, M. Markert, R. Symanczyk, S. Bournat, and Gerhard Mueller.” A Nonvolatile 20Mbit CBRAM Memory Core Featuring Advanced Read And Program Control.” IEEE J. Solid-State Ci

[E2] S. Liu, et al. “Electro-resistive Memory Effect in Colossal Magnetoresistive Films and Performance Enhancement by Post-annealing.” Mat. Res. Soc. Symp. Proc. vol. 648 (2001) P3.26.1-8.



[E3] H. Y. Lee et al, "Lowpower and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM", IEDM 2008 , 297-300

[E4] C. Yoshida et al. "High speed resistive switching in Pt/TiO2/TiN film for nonvolatile memory application", Appl. Phys. Lett. 91 (2007) 223510

[E5] Obtained in ref. [G] from elevated temperature accelerated data retention measurements over 30 h.

[E6] Z. Wei et al., "Highly reliable TaOx ReRAM and direct evidence of redox reaction mechanism", IEDM 2008, 293-296

[E7] Electrochemical cell potentials control the write voltage. In appropriate combinations, 0.5 V will leave some safety margin. Read voltages will be significantly smaller.

[F2] S. T. Hsu, T. Li and N. Awaya. “Resistance Random Access Memory Switching Mechanism.” J. Appl. Phys. 101 (2007) 0245517.

[G2] L. P. Ma, J. Liu, and Y. Yang. “Organic electrical bistable devices and rewritable memory cells” Appl. Phys. Lett. v. 80, no. 16 (2002) 2997-2999.

[H1] A. DeHon, S. C. Goldstein, P. J. Kuekes, P. Lincoln. “Nonphotolithographic nanoscale memory density prospects.” IEEE Trans. Nanotechnol. v. 4, no. 2 (2005) 215-228.

[I1] The number of referred articles in technical journals that appeared in the Science Citation Index database for 7/1/2005–7/1/2007.

[E8] Estimated as E~0.5*V2/RON*tw for V=0.2 Volts, RON=2E5 Ohm , tw=10 ns.

[E9] Estimated based on experimental data reported in Ref. [E1]: E~0.5*V*I*tw , for V=0.6 Volt, I=10mA , tw=50 ns.

[F1] M. Fujimoto et al. “Resistivity and Resistive Switching Properties of Pr0.7 Ca0.3 MnO3 thin Films.” Appl. Phys. Lett. 89 (2006) 243504.

[F3] Y. Watanabe, J.G. Bednorz, A. Bietsch, Ch. Gerber, D. Widmer, A. Beck, S. J. Wind. “Current-driven Insulator-conductor Transition and Non-volatile Memory in Chromium-doped SrTiO3 Single Crystals.” Appl. Phys. Lett. 78, 2001, 3738.

[F4] C. Papagianni, Y. B. Nian, Y. Q. Wang, N. J. Wu, A. Igmatiev, “Impedance Study of Reproducible Switching Memory effect.” Non-Volatile Memory Technology Symposium, 15-17 Nov. 2004, pp. 125-128.

[F5] S. Liu, et al. “Electro-resistive Memory Effect in Colossal Magnetoresistive Films and Performance Enhancement by Post-annealing.” Mat. Res. Soc. Symp. Proc. vol. 648 (2001) P3.26.1-8.

[G1] R. Muller, S. De Jonge, K. Myny, D. J. Wouters, J. Genoe, and P. Heremans. “Organic CuTCNQ integrated in complementary metal oxide semiconductor copper back end-of-line for nonvolatile memory.” Appl. Phys. Lett. 89 (2006) 223501.

[G3] Estimated based on experimental data reported in Ref. [S]: E~0.5*V*I*tw , for , for V=2 Volts, I=10mA , tw=10 ns.

[G4]Ma, L. P., Q. Xu, and Y. Yang. “Organic non-volatile memory by controlling the dynamic copper-ion concentration within organic layer”, Appl. Phys. Lett. 84.24 (2004) 4908–4910.

[H2] W. Wu, G-Y. Jung, D. L. Olynick, J. Straznicky, Z. Li, X. Li, D. A. A. Ohlberg, Y. Chen, S-Y. Wang, J. A. Liddle, W. M. Tong, and R. S. Williams, “One-kilobit cross-bar molecular memory circuits at 30-nm half-pitch fabricated by nanoimprint lithograp

[H3] J. E. Green, J. W. Choi, A. Boukai, Y. Bunimovich, E. Johnston-Halperin, E. Delonno, Y. Luo, B. A. Sheriff, K. Xu, Y. S. Shin, H-R. Tseng, J. F. Stoddart, and J. R. Heath. “A 160-kilobit molecular electronic memory patterned at 1011 bits per square c

[H4] Chen Y., Ohlberg D.A.A., Li XM, Stewart D.R., Williams R.S., Jeppesen J.O., Nielsen K.A., Stoddart J.F., Olynick D.L., Anderson E.. “Nanoscale Molecular-switch Devices Fabricated by Imprint Lithography.” Appl. Phys. Lett 82 (2003) 1610.

[H5] V. Meunier, S. V. Kalinin, and B. G. Sumpter, “Nonvolatile memory elements based on the intercalation of organic molecules inside carbon nanotubes.” Phys. Rev. Lett. 98 (2007) 056401.

Table ERD6 Transition Table for Emerging Research Logic Devices


Technology Entry IN/OUT Reason for IN/OUT Comment

Impact Ionization MOS IN

IN

Tunnel FET IN

Carbon Nanotube FET IN

Graphene Nanoribbon FET IN Bandgap modulation remains a critical issue.

Nanowire FET IN

Ge FET IN

Spin MOSFET IN

Collective spin devices IN Previously called Ferromagnetic devicesPseudospintronic In New concept not in previous edition

Nanomagnetic IN Previously called coherent spin devices

Simulation results showing very low sub threshold slopes indicate potential for low

power operation

Reliability, low voltage operation remain an issue. Included in previous edition transition

table

Nano Electro Mechanical Systems (NEMS)

Potential for ultra low leakage device based on nano relay operation

Issues associated with stiction, speed, active power and reliability are being studied –may

be included in future editions

Potential to utilize gate modulated interband tunneling to reduce subthreshold slope

Low drive current still an issue. Included in previous edition transition table

Included as a category of “1D devices” in previous version

Included as a category of “High Mobility Channel Replacement devices” in previous

version

Included as a category of “1D devices” in previous version

Included as a category of “High Mobility Channel Replacement devices” in previous

version

Included as a category of “spin transistor” in previous version

Table ERD7a MOSFETS:Extending the channel to the End of the Roadmap


Device

FET [A]Typical example devices Si CMOS CNT FET Nanowire III-V FETs Ge FETs

Tri-gate FETGAA FETLocal SOI

Cell Size Projected 15 nm 15nm 100 nm [C]

(spatial pitch) [B] Demonstrated 1.5 µ [J] ~1 µ [K] 40nm [R] 26nm [U] 300 nm [Y]Projected 1.00E+10 4.50E+09 4.50E+09 1.00E+11 1.00E+11 1.00E+11 1E10 [C]

Demonstrated 2.80E+08 4.00E+07 4.00E+07 1.00E+08 1.5E10 [S] 3E10 [V] 4.7E9[Z]

Switch SpeedProjected Not known 6.5 THz [L] Not known Not known 12 THz [C]

Demonstrated 4GHz [G] 250 GHz [M] 2THz [T] 290GHz [W] > 200 GHz[A1]

Circuit SpeedProjected Not known Not known 61GHz [C]

Demonstrated 22 kHz[J] 11.7 MHz [O] Not known Not known 8 GHz[A2]

Switching Energy, JProjected 3.00E-18 3.00E-18 3.00E-18 4E-20 [P] Not known Not known 3.00E-18

Demonstrated 1.00E-16 1E-11 [H] Not known 6.0 E-16 [Q] Not known 4.0E-15 [X] Not knownProjected 238 238 61 1.00E-04 Not known Not known 238

Demonstrated 1.6 1.00E-08 Not known 1.20E-04 Not known Not known Not known

Operational Temperature RT RT RT RT RT RT RT

Materials System Si

CNT,

Graphene

Si, Ge, III-V, II-VI,

InGaAs, InAs, InSb InGaAs, InAs, InSb Ge Research Activity [A3] 240 84 313 167 41 230

Graphene Nanoribbon FET

Unconventional geometries FinFET

100 nm [C] 100 nm [D] 100 nm 30 nm

590 nm ~1.5 mm [E]

Density (device/cm2)

12 THz 6.3 THz [F]1.5 THz 26 GHz[ I]61 GHz 61 GHz [D] 61 GHz [J] 100 GHz [N]5.6 GHz 220 Hz [H]

Binary Throughput, GBit/ns/cm2

In2O3, ZnO, TiO2, SiC



Notes for Table ERD7a:

[A] For Si CMOS entry, parameters for high performance MPU are used: “Projected” (2022), “Demonstrated” (2007).

[B] The effective dimension that one transistor occupies on the MPU chip floor space. For CMOS MPU chips, the relation between cell size and Lg holds approximately constant by scaling: cell size =20Lg.

[D] Size and circuit speed scaling of these structures is the same as the scaling of MOSFETs.

[E] J. Appenzeller, Y.-M. Lin, J. Knoch, P. Avouris. “Band-to-band Tunneling in Carbon Nanotube Field-Effect Transistors.” Phys. Rev. Lett., v. 93, no. 19 (2003) 196805.

[F] P. J. Burke. “AC Performance of Nanoelectronics: Towards a Ballistic THz Nanotube Transistor.” Solid-State Electron. v. 48 (2004) 1981-1986.

[H] A. Javey, Q. Wang, A. Ural, Y.M. Li, H.J. Dai. “Carbon Nanotube Transistor Arrays for Multistage Complementary Logic and Ring Oscillators.” Nano Lett. v. 2, no. 9 (2002) 929–932.

[I] Roman Sordan, Floriano Traversi, Valeria Russo, “ Logic gates with a single graphene transistor”, Appl. Phys. Lett. v. 94, no. 7, 073305 (2009).

[J]Yu-Ming Lin, Keith A. Jenkins, Alberto Valdes-Garcia, Joshua P. Small, Damon B. Farmer, and Phaedon Avouris, “Operation of Graphene Transistors at Gigahertz Frequencies”, Nano Letters, vol. 9 , no. 1,

[K] Y. Huang, X. Duan, Y. Cui, L. J. Lauhon, K.-H. Kim, and C. M. Lieber, “Logic gates and computation from assembled nanowire building blocks,” Science, v. 294, pp. 1313-1317, 9 Nov. 2001.

[L] Y. Li and C.-H. Hwang, “DC baseband and high-frequency characteristics of a silicon nanowire field effect transistor circuit,” Semicond. Sci. Technol., vol. 24, 045004, 2009.

[M] J. Xiang, W. Lu, Y. Hu, Y. Wu, H. Yan, and C. M. Lieber, “Ge/Si nanowire heterostructures as high-performance field-effect transistors,” Nature, vol. 441, pp. 489-493, 2006.

[N] R. Wang, J. Zhuge, R. Huang, Y. Tian, H. Xiao, L. Zhang, C. Li, X. Zhang, and Y. Wang, “Analog/RF performance of Si nanowire MOSFETs and the impact of process variation,” IEEE Trans. Elect. Dev., vol.

[O] R. S. Friedman, M. C. McAlpine, D. S. Ricketts, D. Ham, and C. M. Lieber, “High-speed integrated nanowire circuits,” Nature, vol. 434, no. 7037, p. 1085, Apr. 2005.

[P] J. Knoch, W. Riess, and J. Appenzeller, “Outperforming the conventional scaling rules in the quantum-capacitance limit,” IEEE Elect. Dev. Lett., vol. 29, no. 4, Apr. 2008.

[R] D.-H. Kim et al., “Logic Performance of 40nm InAs HEMTs,” Tech. Dig. of IEDM, p629, 2007.

[S] 1/(80nm*80nm)

[T] Based on the paper [X], CV/I = 0.5ps = 2THz

[C] Lg=5 nm.

[G] A. Le Louarn, F. Kapche, J.-M. Bethoux, H. Happy, G. Dambrine V. Derycke, P. Chenevier, N. Izard, M. F. Goffman, and J.-P. Bourgoin, “Intrinsic current gain cutoff frequency of 30 GHz with carbon nanotube transistors”, Appl. Phys. Lett. 90, 233108, (2007)..

[Q] R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, and M. Radosavljevic, “Benchmarking nanotechnology for high-performance and low-power logic transistor applications,” IEEE Trans. on Nanotechnology, vol. 4, no. 2, Mar. 2005



[U] Ikeda, SSDM 2008.

[V] Based on the gate length of 26nm, the pitch is assumed to be 52nm. The density is calculated with the pitch of 52nm (1/(52nm*52nm)).

[W] J. Mitard et al., “Impact of EOT scaling down to 0.85nm on 70nm Ge-pFETs technology with STI,” VLSI Tech Dig., p82, 2009. Id=1mA/[email protected], Lg=70nm, EOT=0.85nm, CV/I = 3.4ps = 290GHz

[X] Based on the paper [AC], CV*V = 4.0E-15J.

[Y] FinFET with Lg = 15 nm has been reported, and Cell size of 20Lg is employed for Unconventional Geometories.

[Z] Kawasaki H et al.: IEDM Tech. Dig. (2008) 237-280. 0.128 m2 6T FinFET SRAM has been achieved, therefore, the dedicated mean area for one transistor should be 0.128 / 6 = 0.0213 m2

[A1] Kaneko A et al.: IEDM Tech Dig. (2006) 893-896. Sub-5 ps ring oscillator operation has been reported with Dopant-Segregated Schottky S/D FinFET.

[A2] Wanbacq P et al.: ESSDERC Tech. Dig. (2006) 53-56. Tunable oscillator with 45 nm FinFET has been reported with operating frequency of about 8 GHz.

[A3] The number of referred articles in technical journals that appeared in the Science Citation Index database for 7/1/2007–7/1/2009.

Table ERD7b Charge-based Beyond CMOS: Non-Conventional FETs and other charge-based information carrier devices


Device Si CMOSSteep Subthreshold Slope Devices

Spin Transistor NEMSTunnel FET I-MOS Negative Cg FET

Typical example devicesSpin FET [K]

Spin MOSFETCell Size

Projected 20 nm [A] 100 nm 100 nm [X}(spatial pitch) [B] for spin MOSFET [L]

Demonstrated Not known ~200 nm [P,Q] 900 nm

2000 nm for Spin FET[M]

Projected 1.00E+10

Not known:

1.00E+10

~1E10

6.00E+10 1.00E+10for spin MOSFET [L]

Demonstrated 2.80E+08 ~1E10 2.50E+07 Not known Not known ~2E9 1 /cm**2 W2

Switch Speed

Projected Not known 1 GHz [Y]

Demonstrated Not known Not known30GHz

0.18 GHz [Z]

for Spin FET[M]

Circuit Speed

Projected Not known~10GHz or less

1 GHz

DemonstratedNot known:

Not known Not known Not known 1 MHz [T] .18 GHz

Switching Energy, J

Projected 3.00E-18 Not known Not known1E-17-1E-18

5E -17 J [A1,A2]

Demonstrated 1.00E-16 Not known Not known Not known90/90/3000E-18

Projected 238 Not known Not known Not known ~200 10 10

Research Activity [A4] 55 23 2 83 67 47

Single Electron Transistor

Strained Ge or III-V source tunnel FET ,

Heterostructure

Ferroelectric FET [H], [I]

100 nm 100 nm [same as CMOS]

100 nm

40 nm [O]

590 nm Demonstrated: 70 nm, 100nm [B,C]

~1mm (channel length)

Density (device/cm2)1E10[same as

CMOS] [I]channel length

scalable down to 20nm [D]

12 THzIdentical to

CMOSFET- with Ge, SiGe [E],[F],[G]

Not known - Limited by the ferroelectric

response time, depends on the

ferroelectric material

~10 THz or less10 THz [R]for spin MOSFET

[N]]

1.5 THz

Si/Ge/InAs tunneling source:

2 THz [S]1GHz/1THz/3THz

[A]

61 GHzIdentical to

CMOSFET- with Ge, SiGe [E],[F],[G]

Not know - Limited by the ferroelectric

response time, depends on the

ferroelectric material

2 GHz [O]for spin MOSFET [M]

5.6 GHz will depend on the source material used

Identical to CMOSFET- with Ge,

SiGe [E],[F],[G]

1×10–18 [O]for spin MOSFET

[M]] [>1.5×10–17 ] [U]

Si/Ge/InAs tunneling source: 8×10–17 [V]

[>1.3×10–14] [W]J/um at VDD=0.5V,

L=20nm [A]Binary Throughput,

GBit/ns/cm2



Notes for Table ERD7b[A]: Q. Zhang, A. Seabaugh, Can the Interband Tunnel FET Outperform Si CMOS?, DRC 2008, pp. 73-74.

[D]: K. Boucart and A. M. Ionescu, Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric, Solid-State Electronics, Volume 51, Issues 11-12, November-December 2007, pp. 1500-1507.

[H]: S. Salahuddin and S. Datta, “Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices, ” Nanoletters, Vol. 8, No. 2, 2008, pp. 405-410.

[I]: G.A. Salvatore, D. Bouvet, A.M. Ionescu, “Demonstration of subthrehold swing smaller than 60mV/decade in Fe-FET with P(VDF-TrFE)/SiO2 gate stack, ” Techn. Digest of IEDM 2008.

[J] S. Mathews, et.al, "Ferroelectric Field Effect Transistor based on Epitaqxial Perovskite, Science, vol 276, No 5310, P 238-240, April 1997

[K] The evaluations of spin FET in this table are limited for Datta-Das spin FET, although various type of spin FET has been proposed.

[L] The basic structure of spin MOSFET is the same as metal S/D MOSFETs. The same scalability as MOSFETs is expected for spin MOSFET.

[M] S. Bandyopadhyay and M. Cahay, “Reexamination of some spintronic field-effect device concepts”, Appl. Phys. Lett. 85, 1433 (2004)

[P] M.C. Lin, Aravind K., Wu C.S., et al. “Cyclotron Localization in a Sub-10-nm Silicon Quantum Dot Single Electron Transistor.” Appl. Phys. Lett. 90 (3): Art. No. 032106 JAN 15 2007

[B]: W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. King Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Lett., vol. 28, no. 8, Aug. 2007, pp. 743–745.

[C]: T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, “Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With Record High Drive Currents and 60mV/dec Subthreshold Slope”, Tech. Dig. IEEE IEDM, 2008, pp. 947-949.

[E] K. Gopalakrishnan, P.B. Griffin and J. Plummer,”I-MOS: A Novel Semiconductor Device with a Subthreshold Slope lower than kT/q”, IEEE International Electron Devices Meeting, p. 289-292, December 2002.

[F]F. Mayer, C. Le Royer, J.-F. Damlencourt, K. Romanjek, F. Andrieu, C. Tabone, B.Previtali, and S. Deleonibus, “Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance”, IEDM 2008, San Francisco, Dec 15-17, 2008. Digital Object Identifier 10.1109/IEDM.2008.4796641.

[G]F. Mayer, C. Le Royer, G. Le Carval, L. Clavelier and S.Deleonibus, ”Static and Dynamic TCAD Analysis of IMOS Performance: From the Single Device to the Circuit”, IEEE Transaction On Electron Devices, Vol.53, Issue 8, p. 1852-1857, August 2006.

[N] Device/circuit performance of spin MOSFTE is expected to be the same as Si CMOS devices, when the magnetization configuration of the source and drain is parallel. However, the device/circuit performance depends on magnetization configurations of the source and drain. In the antiparallel magnetization configuration, the current drive capability is reduced and thus circuit performance degrades. Note that this magnetization-configuration-dependent output characteristics is essential for reconfigurable logic and nonvolatile logic circuits.

O] For SET logic circuits, device size/density, circuit speed, switching energy and operational temperature are interdependent. The values in the table were derived for a complex circuit operating at 1 GHz: R. H. Chen, A. N. Korotkov, and K. K. Likharev. “Single-electron Transistor Logic.” Appl. Phys. Lett. v. 68, no 14 (1996) 1954.



[Q] M. Hofheinz, Jehl X., Sanquer M., et al. "Simple and controlled Single Electron Transistor Based on Doping Modulation in Silicon Nanowires." Appl. Phys. Lett. 89 (14): Art. No. 143504 OCT 2 2006.

[T]C. Hof, et al. “Manipulating Single Electrons with a Seven-Junction Pump.” IEEE Trans. Instr. Measur. 54 (2005) 670-672.

[W] C. Dubuc, Beauvais J, Drouin D. "Single-electron Transistors with Wide Operating Temperature Range." Applied Physics Letters 90 (11): Art. No. 113104 MAR 12 2007.

[X] Jang et al., “Fabrication and characterization of a nanoelectromechanical switch with 15-nm-thick suspension air gap,” Appl. Phys. Lett. 92, 103110 (2008).

[Y] Kinaret et al., “A carbon-nanotube-based nanorelay,” Appl. Phys. Lett. 82, 1287-1289 (2003).

Z] Kaul et al., “Electromechanical carbon nanotube switches for high- frequency applications,” Nano Lett. 6, 942-947 (2006).

[A1] Pruvost et al., “Design optimization of NEMS switches for suspended- gate single-electron transistor applications,” IEEE Trans. Nanotechnology, 8, 174-184 (2009).

[A2] Yousif et al., “CMOS considerations in nanoelectromechanical carbon nanotube-based switches,” Nanotechnology 19, 285204 (2008).

[A4] The number of referred articles in technical journals that appeared in the Science Citation Index database for 7/1/2007–7/1/2009.

[R]For SET logic circuits, device size/density, circuit speed, switching energy and operational temperature are interdependent. The values in the table were derived for a complex circuit operating at 1 GHz: R. H. Chen, A. N. Korotkov, and K. K. Likharev. “Single-electron Transistor Logic.” Appl. Phys. Lett. v. 68, no 14 (1996) 1954. [P] C. Hof, et al. “Manipulating Single Electrons with a Seven-Junction Pump.” IEEE Trans. Instr. Measur. 54 (2005)

[S]] In notation [Q] above, the reported number of 2 THz for “intrinsic speed” of an experimental SET was derived from capacitance measurements, and not from time-dependent ones. Experimentally, GHz operation was reported in A. Fujiwara et al. “Nanoampere charge pump by single-electron ratchet using silicon nanowire metal-oxide-semiconductor field-effect transistor”, Appl. Phys. Lett. 92 042102 (2008).

[U]The value in the [ ] is the value that includes cooling energy. If an ideal Carnot refrigerator is used for cooling to the operation temperature Tc, the total switching energy ccswTEE300 >, where Ec is the ⋅net switching energy, when cooling energy is not taken into account.

[V] M. Kobayashi, Hiramoto T. "Large Coulomb-blockade Oscillations and Negative Differential Conductance in Silicon Single-Electron Transistors with [100]- and [110]-Directed Channels at Room Temperature." Jap. J. Appl. Phys. Pt 1- 46 (1): 24-27 JAN 2007.

Table ERD7c Alternative Information Processing Devices


Collective spin devices Moving Domain wall Atomic switch Molecular Pseudospintronc Nano magnetic

State Variable Spin metal cations / atoms

Response Function Sinusoidal, various Non linear Non-linear Nonlinear, NDR Non linear

Class—Example Programable logic

Architecture Morphic Morphic Morphic, cross bar Morphic Morphic Morphic

Application Signal Processing Non volitale logic

Comments

Status Demonstrated Simulated Demonstrated Simulated Simulated, theory Demonstrated

Material Issues

Polarization, magnetization

Molecular configuration

Charge distribution symmetry in two

layers

Magneric polarization

patternsGate controlled

NDR

Spin Wave Mach Zender

Ferromagnetic wire devices

Combinatorial logic circuits

Bilayer Pseudospin Field Effent Transistor

MQCA majority gate

Low power, reconfigurable logic

Combinatorial logic circuits

General purpose logic

General purpose logic

Low resistance, low power

Extremely low power

Low power, high density

High propagation loss, slow propagation

velocity

High permeability material required

Low defect bilayer graphene, contacts

Table ERD8 Research and Technology Development Schedule proposed for Carbon-based Nanoelectronics to impact the Industry's Timetable for Scaling Information Processing Technologies


First Year of IC Production 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024CMOS Extension Devices CNT and Graphine Devices

Controlled growth

Chirality of CNTs

Semiconducting vs metallic

n/p Doping Control

Diameter of CNTs

Direction of CNTs

Wall thickness - Single wall

Graphene Epitaxy

Edge Control of Graphene

Bandgap Control of Graphene

Ohmic contacts

Hi-K Gate dielectric & gate metal

Heterobandgap junction structures

Beyond CMOS Devices

Graphine Devices

Narrow Options Pseudospintronics Quantum Interference Quantum Hall Effect Bi-layer structures

This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution.

Research RequiredDevelopment UnderwayQualification / Pre-ProductionContinuous Improvement

CNT Devices

NEMS

Molecular Electronics

Veselago Electron Lens

Table ERD9 Prototypical Criteria for Emerging Device Architectures


Table ERD 10 Summary of the Attributes of Several Emerging Research Devices and Projections for their Application Spaces


Device Token Attributes Potential ApplicationsSpinwave Magnetic Moment Majority gates, parallel data processing

Nanomagnetic Logic (MQCA) Collective Spin

Interband-Tunneling FETs Charge CMOS compatible, low power, fast, scaling limitation Drop-in replacement for CMOS devices

Single Electron Transistors Charge Power/voltage/time efficient Supports Binary Decision Diagram architectures

Spintronic Spin CMOS compatible, self-memory Additions, look-up tablesMagnetic Tunneling Junctions Charge CMOS compatible, nonvolatile Differential circuits, reconfigurable state machines

Graphene-Based SpinFETs Spin/Charge Logically complete General information processingThermal Heat Logic, energy scavenging

Pseudo-spin devices (BISFETS) Pseudospin Digital/binary capable, Boolean Logic design

CMOS compatible, millivolt signals, enables all magnetic circuits

CMOS compatible, natural memory interface to MRAM

Logically complete, systolic/streaming architectures

CMOS compatible, scalable, memory capability, fast, power efficient

CMOS compatible, Volatile sample and hold function, couples to local memory

Table ERD11 Challenges in Existing Memory Systems Illustrated using Today's Memory Devices


Challenges in Existing Memory Systems

Challenge Issues

Power Consumption DRAM consumes 600 mW/Gbps

Memory Hierarchy consumes 30% or more of system power

Bandwidth Multicore requires linear extension of bandwidth with # cores

Power and cost impact of provisioning high bandwidth

Latency Latency management critical in computer design

SRAM SEU rate getting highFlash write limit restricts application range

Universality No Universal device (persistent, fast, small, low power)

Memory device little used outside memory except in configurable logic

Cost

Fill factor (% of memory chip in memory core) too low

Cost per bit must go down dramatically for solid state disk to succeed rotating mediaDRAM and Flash processes too complex to create an integrated SOC device

Table ERD12 Sample of Potential Unique Opportunities for Architectural Exploitation of Emerging Memory Devices


Opportunities for Emerging Memory Devices

Nature of Opportunity Discussion

Energy Optimized Memory Hierarchy Minimize average energy/access from register file to disk

Reorganize memory to minimize power, e.g., Smaller sub-arrays

Exploit 3DIC technology in memory hierarchy

Novel uses of persistent memory Reduce power/area of circuit switched interconnect

Increased use of programmable logic

Embedded checkpointing for reliable computing

Integrate via SOC or 3DIC

CMOL, nano-crossbars and other emerging architectures

Universal memory device

Requires transistorless cell, e.g., 1D1R

Potential for chips with very high device count

Exploit regularity in advanced lithography

In smaller arrays, very low RC in bit/word lines

Smaller arrays for low-power and embedded logic

Need reduction in overhead circuits, especially for small arrays

Many applications don’t need 10 years of retention (e.g., Checkpointing)

Exploiting the 4F2 cell

Table ERD13 Summarizes the Hardware Requirements for the Three Basic Approaches to Probabilistic Inference


Technique Parallelism (Threads) Inter-Thread Communication Computational Precision

Analytic Moderate Moderate High

Random Sampling High Low Moderate

Distributed / Hierarchies High Low Low

Table ERD14 Potential Evaluation for Emerging Research Memory Devices


Table ERD15 Potential Evaluation for Emerging Research Logic and Alternate Information Processsing Devices


Table ERM1 Emerging Research Material Technologies Difficult Challenges


Summary of Issues

III-V has high electron mobility, but low hole mobilityGermanium has high hole mobility, but electron mobility is not as high as III-V materials

Demonstration of high mobility n and p channel alternate channel materials co-integrated with high κ dielectric

Achieving low contact resistance to sub 16nm scale structures (graphene and carbon nanotubes)

Ge dopant thermal activation is much higher than III-V process temperatures

Control of nanostructures and properties

Control of CNT properties, bandgap distribution and metallic fraction

Control of stoichiometry, disorder and vacancy composition in complex metal oxides

Control and identification of nanoscale phase segregation in spin materials

Control of surfaces and interfacesControl of growth and heterointerface strainControl of interface properties (e.g., electromigration)Ability to predict nanocomposite properties based on a “rule of mixtures”

Controlled assembly of nanostructures Control of line width of self-assembled patterning materialsControl of registration and defects in self-assembled materials

Correlation of the interface structure, electronic and spin properties at interfaces with low-dimensional materials

Characterization of low atomic weight structures and defects (e.g., carbon nanotubes, graphitic structures, etc.)

Characterization of spin concentration in materialsCharacterization of vacancy concentration and its effect on the properties of complex oxides

3D molecular and nanomaterial structure property correlation

Characterization of transport of spin polarized electrons across interfaces

Characterization of the structure and electrical interface states in complex oxides

Characterization of the electrical contacts of embedded molecule(s)

Geometry, conformation, and interface roughness in molecular and self-assembled structures

Device structure-related properties, such as ferromagnetic spin and defects

Dopant location and device variability

Difficult Challenges ≤16 nm

Integration of alternate channel materials with high performance

Demonstration of high mobility n and p channel carbon (graphene or carbon nanotubes) FETs with high on-off ratio co-integrated with high κ dielectric and low resistance contacts

Selective growth of alternate channel materials in desired locations with controlled properties and directions on silicon wafers (III-V, Graphene, Carbon nanotubes and semiconductor nanowires)

Growth of high κ dielectrics with unpinned Fermi Level in the alternate channel material

Ability to pattern sub 16nm structures in resist or other manufacturing related patterning materials (resist, imprint, self assembled materials, etc.)

Data and models that enable quantitative structure-property correlations and a robust nanomaterials-by-design capability

Placement of nanostructures, such as CNTs, nanowires, or quantum dots, in precise locations for devices, interconnects, and other electronically useful components

Characterization of nanostructure-property correlations

Characterization of properties of embedded interfaces and matrices

Characterization of the roles of vacancies and hydrogen at the interface of complex oxides and the relation to properties

Fundamental thermodynamic stability and fluctuations of materials and structures

Table ERM2 Applications of Emerging Research Materials


Materials ERD Memory ERD Logic Lithography FEP Interconnects Assembly and Package

Thin Films Tunnel FET: Ge & III-VIMOS: Ge or III-VSpin FET: III-V, Ge

BiSFET: Graphene

Low Dimensional Materials

Nanotubes Electrical applications

Metal nanowires Thermal applications

Mechanical applications

Nanomagnetic MQCA

Macromolecules

Molecular devices Non CAR Resist Novel cleans

Negative tone resist Selective etches Low-κ ILD

Multi-exposure Resists

Single expose dual develop

Selective depositions

Self Assembled Materials

Sub- lithographic patterns Selective etch Selective etch

High performance capacitorsSelective deposition Selective deposition

Deterministic doping

Spin Materials

Spin FETSpin MOSFETCollective Spin DeviceMoving Domain WallNanomagnetic MQCA

1T Fe FET

High performance capacitorsNovel phase change

Charge Trapping Passivation dielectrics

Mott Transition Memory

Ferroelectric Polarization

Nanothermal Oxide

Contacts and interfaces

Alternate Channel CMOS: Ge, III-V, Graphene

Transition metals and nitrides for ultrathin barriers

Nano-electromechanical Memory

Alternate Channel CMOS: Ge, Ge, III-V Nanowires or CNTs

EUV Inorganic-Organic Hybrid Resist (Nanoparticles)

Macromolecular Memory (nanoparticles)

IMOS: Si, Ge or III-V nanowires

Nanothermal (Chalcogenide Nanowire)

SET: Carbon Nanotubes or Semiconductor Nanowires

Graphene and graphitic structures

NEMS Switch: CNT, Nanowires

Molecular memory Macromolecular memory

Self Assembled Molecule Barriers

Polymer electrical and thermal/ mechanical property control

Negative Gate Capacitance FET: FE Polymer

Inorganic-organic hybrid resist

Enhanced dimensional control

Self Assembled Molecule Barriers

STT MRAM Ferromagnetic layers Spin Transport Local

Interconnects TBD

Complex Metal Oxides & Transition Metal Oxides

Magnetoelectric materials (Spin materials)

EUV Inorganic-Organic Hybrid ResistSTT MRAM tunnel barrier &

magnetic pinning layer

Negative Gate Capacitance FET: FE Oxide

Interfaces and Heterointerfaces

Electrical and spin contacts and interfaces

Electrical and spin contacts and interfaces

Electrical contacts and thermal interfaces

Table ERM3 Challenges for ERM in Alternate Channel Applications


Material & Earliest Potenial Insertion Potential Material Value Key Challenges Target/Goal Status

III-V Semiconductors

Achieving low defect density in selective deposition on silicon

Dit<1E12/( eV-cm)

High electron & hole mobility devices Electron mobility >10,000cm2/V-sec [A]

Low contact resistance

Control of stress in process and assembly and packagingStress effects have not been measured yet

Ge

Integration of high κ dielectric with unpinned Ge Fermi level Dit<1E12/( eV-cm)

High hole and electron mobility in a device


Co-integration of III-V and Ge

High electron and hole mobility

Forming low resistance contacts to Ge and III-V compounds

Conductivity must not degrade when embedded in a dielectric


Graphene

High electron mobility

Mobility >8000cm2/V-sec [B]Ability to deposit a high dielectric Dit<1E12/( eV-cm)

Ability to dope the graphene n and p-type

Ability to form low resistance contacts

High electron mobility(InGaAs, InSb) Strained III-V Higher Hole Mobility (Scott UF)

Free of dislocations, twins, phase separation

Dislocations have been reduced but other defects need attention

Integration of high κ dielectric with unpinned III-V Fermi level GdO: Interface control has been achieved by III-V surface passivation and by interface layers

Hole mobility >3000cm2/V-sec Quasi Ballistic Velocity >

Contact Resistivity <1 e-8 W-cm2

Satisfactory gate control has been achieved with standard III-V contact metallurgies

No mobility degradation after assembly & packaging

Adequate hole mobility (~3000cm2/V-sec)*

Fermi level pinning causes are still an open issue

Electron Mobility >10,000 cm2/V-sec Hole mobility >3000cm2/V-sec Quasi Ballistic Velocity >Contact Resistivity <1 e-8 W-cm2 Metal Schottky S/D contacts need to be

investigatedActivating Ge dopants requires higher temperature than III-V processing

Meet 400C implant activation for Ge

Co-implant with He may reduce activation drive-in energy

Explore new Schottky barrier S/D contacts and low-T processing Process compatible Schottky S/D contact

metallurgies need to be investigatedNew scattering effects must be understood in nanoscale channels Work on phonon and interface scattering

just beginningContact Resistivity <1 e-8 W-cm2

Process compatible Schottky S/D contact metallurgies need to be investigated

Ability to deposit graphene (CVD) with controlled orientation and thickness on silicon compatible layers

Develop a new graphene deposition capability that produces the desired film properties and is CMOS compatible No suitable integrated process has been

proposed yetAbility generate a controlled bandgap with high on-off ratio in an integrated structure

Develop new double gate structures for bilayers and controlled lateral dimensions for single layers Bandgap control is still in the discovery

stageAbility to achieve high electron and hole mobility on silicon compatible substrates

Electron Mobility >20,000 cm2/V-sec Hole mobility >10000cm2/V-sec Quasi Ballistic Velocity >

So far only Al2O3 has been formed by oxidation of Al films

Understand elecron/hole puddling physics and edge-dependent doping effects in ambipolar graphene as well as co-deposition of dopants N-doping has been achieved; P-doping still

needs to be demonstratedContact Resistivity <1 e-8 W-cm2

Contact resistances have not yet been eveluated using proper test structures

Table ERM3 Challenges for ERM in Alternate Channel Applications


Material & Earliest Potenial Insertion Potential Material Value Key Challenges Target/Goal Status

Si or Ge Nanowires

Ability to grow nanowires in desired locations and directions

Catalyst compatible with CMOS processing

Ability dope nanowire channel and S/D regions

Ability to achieve high electron and hole mobility on silicon

Ability to pattern surround gate structures

III-V Nanowires

Ability to grow nanowires in desired locations and directions


Ability dope nanowire channel and S/D regions




Carbon Nanotube FETs


Ability to grow CNTs in desired locations and directions

Ability dope CNT channel and S/D regions




* Field Effect MobilityReferences for Table ERM3

High gate control of leakage current and possibly low surface surface scattering

Selectively deposit NW's in either vertical or horizontal locations

Initial NW deposition in controlled locations has been demonstrated but not for monolithic processing

Metal catalysts cannot introduce deep level defects into the channels and S/D's


Demonstrate conrolled doping of NW's wirh atomically sharp boundaries Initial co-linear and surround NW doped

sructures have been grown by CVD on a one-ff basis but not monolithically

Identify and understand mobility degradation processes in NW's Mobilities of 50% of bulk values have been

achieved in Si and Ge NW's

Develop fabrication methods for surround gates for both vertical and hoizontal NW's

Individual NW structures have been demonstrated but monolithic processing has not

High electron mobility with high gate control of leakage current

Selectively deposit NW's in either vertical or horizontal locations



No data yet on catalyst effects on NW FET performance

Demonstrate conrolled doping of NW's with atomically sharp boundaries

Initial co-linear and surround NW doped sructures have been grown by CVD on a one-ff basis but not monolithically

Identify and understand mobility degradation processes in NW's

Mobilities of 50% of bulk values have been achieved in individual AlGaAs NW's but not on Si

Devlop fabrication methods for both vertical and horizontal FET's

Individual NW structures have been demonstrated but monolithic processing has not

Contact resistances cannot modulate channel transport Low values have been achieved with Pt but

not for CMOS process compatible metallurgies

High mobility with high gate control of leakage current


No data yet on catalyst effects on CNTW FET performance

Ability to grow CNTs in planar structures with density compatible with sub 15 nm technology Ability to grow CNTs with catalyst on

quartz or shapphire with density of 10 per micrometer

Demonstrate conrolled doping of NW's with atomically sharp boundaries

Initial co-linear and surround CNT doped sructures have been grown by CVD on a one-ff basis but not monolithically

Identify and understand mobility degradation processes in NW's Fully integrated CNT channels on CMOS

have not been demonstrated yet

Devlop fabrication methods for both vertical and horizontal FET's

Individual CNT structures have been deposited on a planar gate dielectric but fully integrated channels have not been demonstrated

Contact resistances cannot modulate channel transport Low resistance contacts have been

demonstrated but materials compatibility with CMOS processing has not been demonstrated yet

[A] M. K. Hudait, G. Dewey, S. Datta, J. M. Fastenau*, J. Kavalieros, W. K. Liu*, D. Lubyshev*, R. Pillarisetty, W. Rachmady, M. Radosavljevic, T. Rakshit and Robert Chau. Heterogeneous Integration of Enhancement Mode In0.7Ga0.3As Quantum Well Transistor on Silicon Substrate using Thin (=2um) Composite Buffer Architecture for High-Speed and Low-Voltage (0.5V) Logic Applications,” International Electron Devices Meeting (IEDM) Technical Digest, 2007, pp. 625-628.

[B] S. Kim,_J. Nah, I. Jo, D. Shahrjerdi, L. Colombo, Z. Yao, E. Tutuc, and S.K. Banerjee. “Realization of a high mobility dual-gated graphene field-effect transistor with Al2O3 dielectric.” Applied Physics Letters, vol. 94, pp. 062107, 2009.

Table ERM9 Alternate Channel Materials Critical Assessment


N=8 Raters Research targets

3 1.8 1.5 2 2

3

2

1

III-V Materials (2019+) 3 1.8 1.1 1.6 2

3

2

1

2.6 1.8 1.6 1.3 1.8

3

2

1

3 1.8 1.3 1.4 1.3

3

2

1

Graphene (2019+) 2.9 1.7 1.3 1.4 1.4

3

2

1

Mobilities: Hole >5000 cm2/ V-s

and/or Electron >5000 cm2/V-s

Performance Unpinned Fermi level, 10% thickness (1s),

Dit <1E12/(eV-cm2)

Material grown on Si wafers with low defect

density

Contact resistivity <1E-8 W-cm2

Property Control

10% (1s)

Ge [For p-channel devices](2013-2018)

Homogeneous Nanowires [Group IV and III-V] (2019+)

Carbon Nanotubes(2019+)

Table ERM9 Alternate Channel Materials Critical Assessment


N=8 Raters Research targets

3

2

1

III-V Materials (2019+)

3

2

1

3

2

1

3

2

1

Graphene (2019+)

3

2

1

Ge [For p-channel devices](2013-2018)

Homogeneous Nanowires [Group IV and III-V] (2019+)

Carbon Nanotubes(2019+)

1.8 1.8 1.8 1.8

1.6 1.6 1.7 1.6

1.8 1.6 1.7 1.7

1.3 1.4 1.3 1.4

1.4 1.4 1 1.4

Demonstrate /understand controlled n and/or p channel & S/D doping, e.g. 10%

(1s)

CMOS compatible catalyst, as needed,

10% of half pitch, vert. and/or horizontal

Understand formation mechanism, develop

low defect density strategy

Integration Average (excluding mobility)

Table ERM5 Spin Material Properties


Application Requirements Ferromagnetic Metal Half Metals

Ferromagnetic Spin Injector LSMO Tc=350

High injection efficiency Excellent below Tc Excellent below Tc

Resistance Mismatch High Schottky Barrier TBD Low Low LowNo direct ability High Coupling below Tc Unknown

Oxide Dielectrics Other Dielectrics Complex Metal Oxides

Spin tunnel barrier TMR% >1000% MgO ~ 70%@300ºK[A]

AlN

Half Metals

Magnetoelectric Switch None Reported

Operation >400K

Silicon Graphene and CNTs III-V

Spin Torque & Transport Spin coherence time or length

Compound Ferromagnetic Metals

Dilute Magnetic Semiconductor

Wide Bandgap Magnetic

Semiconductors

High Remnant Magnetization (>400K)

Co, Fe, Ni and alloys >50% RM 400K

Cu2MnAl, Cu2MnSi, etc. Ga(Mn(As) Tc 195K

TiO2: Co, SnO2:Co, etc.

Acceptable through Schottky Barrier and tunnel dielectric

Unknown: Low Carrier Mobility

Ability to modulate magnetization with electric potential

High Coupling below Tc

CaF2 LSMO/LAO/LSMO ~150% @10ºK[C]

Al2O3 ~ 1-20% @300ºK[B]

Dilute Magnetic Semiconductors

Complex Metal Oxides (MagnetoElectric)

High Coupling of Electric Field to Magnetization

(GaMn)N: 300ºK; Saturation Magnetization=3µemu [D]

BiFeO3:CoFe: Saturation magnetization >1000emu/cc[E] (300ºK)

Candidates: -Complex Metal Oxide Heterostructures (e.g.STO-LAO, etc.) -Huesler Alloys (e.g. Cu2MnAl, CuMnSi, etc.)

10microns; 100microseconds (85ºK)[F]

Graphene: 1.5-2 microns(300ºK) [G] CNT >130nm (20ºK)[H]

Table ERM5 Spin Material Properties


References for Table ERM5:

[F] B. Huang, D.J. Monsma, I. Appelbaum. "Experimental realization of a silicon spin field-effect transistor." Appl. Phys. Lett., vol. 91, pp. 072501, 2007.

[G] N. Tombros, C. Jozsa, M. Popinciuc, H.T. Jonkman, and B.J. van Wees. "Electronic spin transport and spin precession in single graphene layers at room temperature.", Nature, vol. 448, pp. 571-574, 2007.

[H] K. Tsukagoshi, B.W. Alphenaar, and H. Ago, "Coherent transport of electron spin in a ferromagnetically contacted carbon nanotube." Nature, vol. 401, pp. 572, 1999.

[A] Z. Diao, A. Panchula, Y. Ding, M. Pakala, S. Wang, Z. Li, D. Apalkov, H. Nagai, A. Driskill-Smith, L.-C. Wang, E. Chen, and Y. Huai. "Spin transfer switching in dual MgO magnetic tunnel junctions." Appl. Phys. Lett., vol. 90, pp. 132508, 2007.

[B] Y. Huai, F. Albert, P. Nguyen, M. Pakala, and T. Valet. "Observation of spin-transfer switching in deep submicron-sizedand low-resistance magnetic tunnel junctions." Appl. Phys. Lett., vol. 84, pp. 3118, 2004.

[C] Y. Ishii, H. Yamada, H. Sato, and H. Akoh, M. Kawasaki, Y. Tokura. "Perovskite manganite magnetic tunnel junctions with enhanced coercivitycontrast." Appl. Phys. Lett., vol. 87, pp. 022509, 2005.

[D] N. Nepal, M. Oliver Luen, J.M. Zavada, S.M. Bedair, P. Frajtag, and N. A. El-Masry. "Electric field control of room temperature ferromagnetism in III-N dilute magnetic semiconductor films.", Appl. Phys. Lett., vol. 94, pp. 132505, 2009.

[E] L.W. Martin, Y.-H. Chu, M.B. Holcomb, M. Huijben, P. Yu, S.-J. Han, D. Lee, S.X. Wang, and R. Ramesh. "Nanoscale Control of Exchange Bias with BiFeO3 Thin Films." Nano Letters, vol. 8, pp. 2050-2055, 2008.

Table ERM6 ERM Memory Material Challenges


Table ERM6 ERM Memory Material ChallengesApplication Material Potential Advantage Key Challenges Goal/Target Status

Ferroelectric FET

Complex Metal Oxides

Depolarisation field - control of charge trapping

Memory retention time and fatigue - choice of metallic electrode

Nanoelectromechanical Memory

High on/off ratioOperation below 1V

Contact reliability due to frictional wear in switching >1E9 cycles

ScalabilityReliable operation Nonhermetic packaging

STT MRAM

Ferromagnetic Metal: Co-FeTBD

Tunnel Barrier: MgO High spin selectivity Identifying a tunnel barrier with higher spin selectivity TMR>1000% MgO~70%

1E12 cycles

Macromolecular Memory Polymer Low Cost Reliable switching mechanism 1E5 Cycles >1E6 cyclesMetallic Nanoparticles Determine the scalability of charge storage with nanoparticle size

Molecular Memories

Molecules High Density Reliable switching mechanism 1E5 Cycles ~2E3 cycles

Contact metal Deposition of the top electrode without changing the moleculeTBD

Contacts that don't migrate in the applied fields No metal migration

Interface with silicon - defects at interfaces - compatibility with silicon Dit<1E11cm-2

data retention 10 years at 55°C

cycling endurance 1E5 write

choice of gate first/gate last for processing with regarding thermal budget

Carbon Nanotubes or patterned thin film structures

Stiction required for a stable state requires high voltage for switching.

Cycling endurance 1E5 write

High remnant magnetization

Scaling the etch process to small dimensions without shorting the tunnel barrier

Pinning Layer: Complex Metal Oxide

Low leakage passivation of tunnel barrier: stable through 1E5 Write Cycles

<10% increase in 1E5cycles

ITWGINDEX

Table ERM6 ERM Memory Material Challenges


Application Material Potential Advantage Key Challenges Goal/Target Status

Electronic Effects Memory

Charge Injection and StorageScalability

Nonvolatile

Mott Effect Memory

FE Barrier

End of Electronic Effects Memory

Nanothermal Memory

Mechanism to decrease power for thermal switch

Higher thermal resistance Growth of the nanowires with controlled diameter

Transition metal oxides

Determine scalability and reliability of the technology

Nano Ionic Memory

Complex Metal Oxides Improve the stability of the eletrochemical reaction

Reference for Table ERM6

Transition Metal Oxides: e.g. Cu2O

Determining the charge storage mechanism, its scalability and long term reliability

Complex Metal Oxides: e.g. Pr0.7Ca0.3MnO3

Determining the charge storage mechanism and its scalability Understanding the role of vacancies and reproducibly controling their concentration

Complex Metal Oxides and Transition Metal Oxides: e.g. Nd1-

xSrxMnO3 and VO2

Scalability and nonvolatility

Determining whether the electronic transition can reversibly occur with or without the first order structural phase transition. Determining the thermal control required for reverisible operation

Complex Metal Oxides: e.g. BaTiO3

Scalability and nonvolatility Developing reliable reproducible interfaces between the tunnel

barrier and the FE. Determining whether this transition can reproducibly occur in polycrystalline material

Chalcogenides (GeSbTe, etc.) Lower switching energy than thin films


Determine the relationship between the material-related process (e.g. deposition, etching processes) and the reliablity of the memory performance (e.g. endurance, retention)

Cycling endurance 1E5 write

>1E9 cycles [A] Retention >10 yrs at 85°C


Mechanism to decrease required power for the electrochemical reaction

[A] Z. Wei, Y. Kanzawa, K. Arita, Y. Katoh, K. Kawai, S. Muraoka, S. Mitani, S. Fujii, K.Katayama, M. Iijima, T. Mikawa, T. Ninomiya, R. Miyanaga, Y. Kawashima, K. Tsuji, A. Himeno, T. Okada, R. Azuma, K. Shimakawa, H. Sugaya, and T. Takagi, R. Yasuhara, K.Horiba, H. Kumigashira, and M. Oshima. “Highly Reliable TaOx ReRAM and Direct Evidence of Redox Reaction Mechanism.”Tech. Dig. Int. Electron Devices Meet., 2008, pp.293-296, 2008.

Table ERM7 Challenges for Lithography Materials


Application Material/ Process Potential Value Key Challenges Status

193nm Extension Positive Chemically Amplified Resist Evolutionary Solution No ERM

Positive Non Chemically Amplified Resist Potential decoupling of resolution & LER

Negative Tone Resist Reduce LER with high resoution 50nm L/S process margin close to positive resist[b]

193nm Pitch Division Spacer Patterning Use Conventional Materials No ERM

Double Pattern Use Conventional Resist Pattern collapse margin No ERMSingle Expose Two Tone Develop Single Exposure and single track operation

Double Exposure Resist Single Track Double Exposure

EUV Resist Positive Chemically Amplified Resist Evolutionary Solution No ERM

Negative Tone Cationic Resist Reduced Sensitivity to Flare Microbridging and pattern collapse margin*

Negative Tone Non Chemically Amplified Resist Reduced outgassing

Inorganic and Inorganic-Organic Hybrid Resist High contrast and resistance to pattern collapse

Non Chemically Amplified Resist Reduced outgassing Resolution of 35nm L/S[j]

Best Reported

Directed Self Assembly Lithography Extension

*Pattern collapse solutions need to be simple to implement or use existing process base

Ability to simultaneously achieve resolution, sensitivity, line edge roughness and pattern collapse margin

Requires a high intinsity image and need to improve etch resistance and pattern collapse margin

E0<50mJ/cm2[a]

Poor performance with phase shift mask, microbridging, and pattern collapse margin

Multiple process steps and lithography steps required. Pattern collapse margin

Achieving symmetric feature spacings with postive and negative tone developers and pattern collapse margin

38nm L/S demonstrated with low LER and improved CD uniformity with 1.07NA 193nm Immersion[c]

Identifying a two exposure molecule (D2) that reverts to the initial state without the second exposure and integrating in a resist in the required timeframe and pattern collapse margin*

Modified tethered bromo-anthracene system showed evidence of D2 behavior in solution, and apparent reversibility without acid release[d]: Need to demonstrate in resist

Ability to simultaneously achieve (resolution, sensitivity, line edge roughness and pattern collapse margin*

Molecular Glass(MG) Fullerene achieved 20nm hp with LER 2.5-4.5nm with e-beam (11μC/cm2)[e], MG-Epoxide achieved 25nm hp with low LER e-beam (38 to 22 μC/cm2)[f]

Achieving resolution, senstivity, LER, etch resistance without microbridging, and pattern collapse margin*

Resolved 60nm isolated lines with EUV exposure of 5-6 mJ/cm2 with lower outgassing than SELETE Std.[g]

Achieving resolution, senstivity, LER,, and potential defectivity issues with inorganic materials

HSQ printed 20nm hp and LER<2nm with EUV interference [h] Zr and Hf based resist printed 36nm hp LER <2nm and RIE etch resistance 7X higher than thermal SiO2 [i]

Achieving required sensitivity, resolution, etch resistance, and pattern collapse margin*

1. Neutral Surface Layer 2. Assembly Control -Graphoepitaxy -Surface Chemical Pattern -Hybrid Resist 3. Supramolecular Options -Di or Tri Block Co-polymers -Di or Tri Block-co-polymer/monomer mixtures 4. Fast Annealing Options -Above Tg -Solvent Annealing

>Higher density features than lithography >Reduced line edge roughness

>Ability to generate required features at a minimum of 2× higher density than achievable by best direct lithographic methods >Ability to achieve low defect density >Annealing times of a few minutes for all patterns >Reducing process complexity >Ability to align features to previous structures >Etch selectivity

Minimum Feature Size: 7 nm (lamellar pattern)[k] LER: 2.2 nm (on 24 nm linewidth lamellar pattern)[l] Defect Density: 1 part in 10000 (sparse chemical patterning of hexagonal array of cylinders) [m] Minimum Annealing Time: 1 minute (dense chemical patterning of lamellar structure [n] Patterns Demonstrated (Y/N) Double Density Lines Y [o] Double Density Square Contacts N Isolated Lines Y [o] Isolated Contacts Y [p]

Table ERM7 Challenges for Lithography Materials


References

[e] J. Manyam, M. Manickam, J.A. Preece, R.E. Palmer, A.P.G. Robinson. “Low Activation Energy Fullerene Molecular Resist.” SPIE, vol. 7273, pp. 72733D, 2009.

[f] R.A. Lawson, L.M. Tolbert, T.R. Younkin, C.L. Henderson, “Negative-Tone Molecular Resists Based on Cationic Polymerization.” SPIE, vol. 7273, pp. 72733E, 2009.

[g] M. Shirai, K. Maki, H. Okamura, K. Kaneyama, T. Itani. “Non-Chemically Amplified Negative Resist for EUV Lithography.” SPIE, vol. 7273, pp. 72731N, 2009.

[i] J. Stowers, D.A. Keszler. “High resolution, high sensitivity inorganic resists.” Microelectronic Engineering, vol. 86, pp. 730-733, 2009.

[a] I. Blakey, L. Chen, Y. Goh, K. Lawrie, Y. Chuang, E. Piscani, P. A. Zimmerman and A.K. Whittaker. “Non-CA Resists for 193 nm Immersion Lithography: Effects of Chemical Structure on Sensitivity.” SPIE, vol. 7273,pp. 72733X, 2009.

[b] T. Ando, S. Abe, R. Takasu, J. Iwashita, S. Matsumaru, R. Watababe, K. Hirahara, Y. Suzuki, M. Tsukano and T. Iwai. ”Topcoat-free ArF Negative Tone Resist.” SPIE, vol. 7273, pp. 727308, 2009.

[c] S. Tarutani, T. Hideaki, and S. Kamimura. “Development of materials and processes for negative tone development toward 32-nm node 193-nm immersion double-patterning process.” SPIE, vol. 7273, pp. 72730C, 2009.

[d] R. Bristol, D. Shykind, S. Kim, Y. Borodovsky, E. Schwartz, C. Turner, G. Masson, K. Min, K. Esswein, J.M. Blackwell, N. Suetin. “Double-Exposure Materials for Pitch Division with 193nm Lithography: Requirements, Results.” Proc. SPIE, vol. 7273, pp. 727307, 2009.

[h] Y. Ekinci, H.H. Solak, C. Padeste, J. Gobrecht, M.P. Stoykovich, P.F. Nealey. “20 nm Line/space patterns in HSQ fabricated by EUV interference lithography.” Microelectronic Engineering, vol. 84, pp. 700, 2007.

[j] A.K. Whittaker, I. Blakey, J. Blinco, K.S. Jack, K. Lawrie, H. Liu, A. Yu, M. Leeson, W. Yeuh, T. Younkin. “Development of Polymers for Non-CAR Resists for EUV Lithography.” SPIE, vol. 7273, pp. 727321, 2009.

[k] "Patterning sub-10 nm line patterns from a block copolymer hybrid", Sang-Min Park, Oun-Ho Park, Joy Y Cheng, Charles T Rettner and Ho-Cheol Kim, Nanotechnology 19 455304 (2008).

[l] "Pattern transfer using poly(styrene-block-methyl methacrylate) copolymerfilms and reactive ion etching" Chi-Chun Liu , Paul F. Nealey, Yuk-Hong Ting and Amy E. Wendt, J. Vac. Sci. Technol. B 25 1963 (2007).

[m] "Density Multiplication and Improved Lithography by Directed Block Copolymer Assembly", Ricardo Ruiz,Huiman Kang, François A. Detcheverry, Elizabeth Dobisz,Dan S. Kercher, Thomas R. Albrecht, Juan J. de Pablo and Paul F. Nealey, Science 321, 936 (2008)

[n] Rapid Directed Assembly of Block Copolymer Films at Elevated Temperatures" Adam M. Welander, Huiman Kang, Karl O. Stuen, Harun H. Solak, Marcus Müller, Juan J. de Pablo and Paul F. Nealey, Macromolecules 41, 2759 (2008) :

[o] Directed Self-Assembly of Block Copolymers for Nanolithography: Fabrication of Isolated Features and Essential Integrated Circuit Geometries, Mark P. Stoykovich, Huiman Kang, Kostas Ch. Daoulas, Guoliang Liu, Chi-Chun Liu, Juan J. de Pablo,Marcus Müller and Paul F. Nealey, ACS Nano, 1, 168 (2007).

[p] Creation of sub-20-nm contact using diblock copolymer on a 300 mm wafer for complementary metal oxide semiconductor applications, Wai-kin Li and Sam Yang, J. Vac Sci Tch B 25 1982 (2007)

Table ERM8 FEP / PIDS Challenges for Self Assembly


Application Potential Value Key Challenges Target/Goal Status

Deterministic Doping

TBD

Abrupt S/D interface doping with controlled gradient Table FEP12

TBD

TBD

TBDTBD

Selective EtchTBD

Clean and Surface Prep

Contacts Lower contact resistivity TBD

Reduced variation in transistor performance Highest focus will be on S/D dopant latteral abruptness (Maintain high concentration of active dopants with an abrupt transition)

Ability to pattern dopant array with periodicity required for device operation

Understanding a mechanism to reproducibly introduce dopant from self assembled material into transistor structuresDemonstrate potential to satisfy throughput requirementsDemonstrating potential to satisfy integration and manufacturing requirements

Ability to selectively protect materials during etch or cleaning operations

Ability to design polymer brushes to selectively coat and protect new materials against chemical etches

Low defect densityCompatility with existing cleansEasy removal

Uniformity compatibility with silicon CMOS Materials

Table ERM9 Interconnect Material Challenges


Application Potential Value Key Challenges Target/Goal Status

New Transition Metal Nitrides

< 2nm

~ 5nm ZrN

5nm + 5nm TaN

6nm NiB

a-C:H, BCN, Reduce interconnect capacitance k < 4

Low k ILD

Nanoporous ILD

Reduce interconnect capacitance

k < 2

Novel Polymers

Air Gap Materials

Barrier Layers (Via/Trench) for Copper Interconnects

Extend Copper Interconnects and Minimize Resistivity Degradation

Thickness Scaling & Barrier Performance at < 2nm

PVD Direct Plate Barriers (Ir, Os, Rh, ...)

Adhesion to low-k ILD or air gap materials and Cu, Barrier Performance at < 2 nm

Self Assembled Monolayers (SAM)

Adhesion to low-k ILD and Cu, Barrier Performance over topography / rough surfaces, Susceptibility to Thermal/Plasma Damage

SAM + Electroplate Boride/Phosphide

Adhesion to low-k ILD and Cu, Barrier Performance at < 2 nm

Capping Barrier Layers for Copper Interconnects

Adhesion to low-k ILD and Cu, Barrier Performance and Leakage Currents at < 2 nm

Mechanical Strength, Adhesion, Leakage Current, Compatibility with patterning, metallization, and packaging processes

Mesoporous ILD - k < 2.0 (Zeolite, Aerogel, ...)

Mechanical Strength, Adhesion, Leakage Current, Compatibility with patterning, metallization, and packaging processes

Mechanical strength, Adhesion, Thermal Stress (CTE) & Stability, Swelling, Leakage Current

Air Gap Pinch Off/Formation Control, Air Gap Stability, Barrier Integrity, Conformality/Step Coverage

keff < 2

Table ERM10 Nanomaterial Interconnect Material Properties


Application Requirements

Vias

High density in small vias

No data available on the density

Defect-free metal contacts

Effective Resistivity

No Data Availiable.

Control of chirality

Only purification in liquid to date. [D] Not Applicable, all MWCNTs are metallic

Thermal behavior

Carbon Nanotubes (Single Walled)

Challenges


Status

Carbon Nanotubes (Multiwalled) Challenges

Carbon Nanotubes (Multiwalled)

Status

1E14 metallic tubes/cm2 inter-tube distance: 0.68 nm; tube diameter < 1.1 nm. Need to develop new catalytic systems.

Need of 5-10E12 tubes/cm2, tube diameter <5-3 nm

Ability to grow in-situ and integrate 1E12 vertically aligned tubes/cm2 in 150 nm vias with repeatable yield[A]

Need reliable and reproducible ohmic contacts. Contacting SWCNTs with diameter <1.5 nm needs to be improved.

Pd to date is the best metal to contact nanotubes.[B]

Need to produce direct metallic contacts to all the shells to minimize risks of resistance, local heating, and electromigration.

Pd to date is the best metal to contact nanotubes.[B]

Need to increase metallic content. Need to understand how defects, structure and dielectric interface affect nanotube resistance.

Must achieve a high density of MWNTs and a low contact resistance between CNTs and metal contacts.

Resistances down to 0.6 Ohm in 2 µm diameter vias filled with MWCNTs have been reported; lowest documented resistance for an array of MWCNTs in a 2.8 µm (60 nm high) via is 0.05 Ohm.[C]

Need a process and catalyst to grow dense arrays of metallic SWCNTs with diameter < 1.1 nm. Need to achieve accurate control of chirality distribution.

Not an Issue: All MWCNTs behavior is metallic.

Needs experiments to determine thermal conductivity of CNT vias. Reduce thermal interface resistance.

No Data Availiable. Intrinsic CNT thermal resistance is low. Thermal interface resistance may limit performance

Need to increase density of MWNTs.Need to decrease thermal resistance between CNTs and contacts

No Data Availiable Intrinsic CNT thermal resistance is low. Thermal interface resistance may limit performance



Application Requirements Carbon Nanotubes (Single Walled)

Challenges


Status



Status

Interconnects

Defect-free metal contactsNo progress reported No progress reported

Control of chirality Same as for vias Not an Issue All MWCNTs are metallic

Thermal behaviour Same as for vias No progress reported Same as for vias No progress reported

Effective resistivity

No progress reported No progress reported

Ability to grow in controlled locations

Need to achieve same densities of metallic SWCNTs as with vertical vias.

CNTs can be grown in specific locations with patterned catalyst[E] CNTs have been grown horizontally in templating materials (e.g. zeolites, etc.)[F] The big issue is growing them in predefined directions.

Need to achieve same densities of MWCNTs as per vertical vias.

CNTs can be grown in specific locations with patterned catalyst. [E] The big issue is growing them in predefined directions.

Ability to grow in controlled directions

Over long distances (> 20 µm) alignment <200 arcsec is required.

Growth in a zeolite template may be most compatible with interconnects, but has a very low maturity.[F] Other options: Growth in electrical field: Low accuracy [G] Growth along quartz crystal steps: may be difficult to apply to interconnects. [H] Need faster CNT growth rate.

Need to achieve same high densities of MWCNTs as per vertical vias to achieve a bundle growth.Need to increase the growth speed of MWNTs at a low CVD growth temperature..

Directional growth of a bundles of MWNTs is reported. Need higher growth rate. [I]

Same as for the vias, but more difficult with horizontal interconnects.

Same as for vias, but more difficult with horizontal interconnects.

Progress reported in liquid purification, but requires ex-situ assembly [D]

Need to achieve nanotube densities in same orders of magnitude as for vias.

Need to achieve same densities of MWCNTs as with vertical vias.Need to improve the quality of CNTs to achieve longer ballistic length.



Application Requirements Carbon Nanotubes (Single Walled)

Challenges


Status



Status

References for Table ERM10

[A] Y. Awano, Proc. of Selete Symposium (in Japanese) (2008)

[B] W. Kim, A. Javey, R. Tu, J. Cao, Q. Wang, and H. Dai. “Electrical contacts to carbon nanotubes down to 1 nm in diameter.” Appl. Phys. Lett., vol. 87, pp. 173101, 2005.

[F] N. Wang, Z. K. Tang, G. D. Li and J. S. Chen. “Single-walled 4 Å carbon nanotube arrays.” Nature, vol. 408, pp. 50, 2000.

[G] A. Ural, Y. Li, and H. Dai. “Electric-field-aligned growth of single-walled carbon nanotubes on surfaces.” Appl. Phys. Lett., vol. 81, pp. 3464, 2002.

[C] D. Yokoyama, T. Iwasaki, T. Yoshida, H. Kawarada. “Low temperature grown carbon nanotube interconnects using inner shells by chemical mechanical polishing.” Appl. Phys. Lett., vol. 91, pp. 263101, 2007.

[D] M.S. Arnold, A.A. Green, J.F. Hulvat, S.I. Stupp, and M.C. Hersam. “Sorting carbon nanotubes by electronic structure using density differentiation.” Nature Nanotechnology, vol. 1, pp. 60-65, 2006.

[E] A. Javi and H. Dai. "Regular Arrays of 2 nm Metal Nanoparticles for Deterministic Synthesis of Nanomaterials." Journal of the American Chemical Society, vol. 127, pp. 11942-11943, 2005.

[H] K. Ryu, A. Badmaev, C. Wang, A. Lin, N. Patil, L. Gomez, A. Kumar, S. Mitra, H. S. P. Wong, and C. Zhou. “CMOS-Analogous Wafer-Scale Nanotube-on-Insulator Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes.” Nano Letters, vol. 9, pp. 189, 2009.

[I] Y. Awano, “Carbon Nanotube Technologies for LSI via Interconnects ”, IEICE Transactions on Electronics E89-C(11), pp.1499-1503, 2006 or M. Nihei, D. Kondo, A. Kawabata, S. Sato, H. Shioya, M. Sakaue, T. Iwai, M. Ohfuti and Y. Awano, “Low-resistance multi-walled carbon nanotube vias with parallel channel conduction of inner shells”, IEEE 2005 International Interconnect Technology Conference, pp.234-6, 2005.

Table ERM11 Assemby and Packaging ERM Challenges


Table ERM11 Assemby and Packaging ERM ChallengesApplication ERM Important Properties Key Challenges Target/Goal Status

Low Temperature Assembly

Nanosolder

Not achieved yet

Not achieved yet

High Performance Chip Attach Nanotubes

Not achieved yet

Stacked Chip Adhesives (Low power density) low CTE systems

Melting point, latent heat reduction of solders

Oxidation free solder nanoparticles < 5nm with a tight distribution; Demonstration of melting point reduction in macro-scale; Demonstration of first or second level interconnect solder joint at low temperatures (< 200°C)

Oxide free < 5nm NPs, FLI or SLI solder joint demonstrated at temperatures < 200°C

Electrically conductive adhesives with metallic nano-fillers embedded in an epoxy matrix

Cured at temperatures ~175ºC, but can withstand 260°C reflow. Compatible with MSL2.

unstable contact resistance, poor impact performance, lower electrical and thermal conductivity, poor current carrying capability and metal migration compared to Pb-free solders

High current carrying capacity, high electro-migration resistance

Low electromigration resistance of metals [Copper and solder] at high current densities > 106 A/cm2, alternate materials like carbon nanotubes have high current carrying capacity but show high contact resistance and integration of nanotubes into packages is difficult

Show ease of integration of nanotubes [low temperature growth or efficient transfer]; lower nanotube contact resistance

Die attach materials/back side films, materials for thin packages

Using nanoparticles, low BLTs can be achieved and by increasing their loading, CTE can be lowered, but the viscosity goes up upon addition of nanoparticles and their dispersion is difficult to control at high loadings

Control dispersion, dispensability of nanoparticle based composites at high loading

Some progress for oxide based nanoparticles but for limited set of filler-matrix systems

ITWGINDEX

Table ERM11 Assemby and Packaging ERM Challenges


Application ERM Important Properties Key Challenges Target/Goal Status

Stacked Chip Adhesives (High power density) low BLT, low CTE, high K Reducing thermal interface resistance Not achieved yet

Underfill Next generation underfill

Mold Compound Next generation MC

New polymer with nanofillers

Decoupling Capacitors

>1 micron=thick film<1 micron=thin filmMoisture at particle-polymer interface and interfacial adhesion is a critical issue

Better cooling solutions with low thickness

Lower viscosity polymers with low CTE (10-14ppm), and have low shrinkage post cure

Using nanoparticles, low CTEs can be achieved, but the viscosity goes up upon addition of nanoparticles and their dispersion is difficult to control at high loadings. Effective resin shrinkage maybe prevented by adding large enough amount of nanoparticles, but the downside to that is viscosity increase at high filler loadings

Control dispersion, dispensability of nanoparticle based composites at high loading

Some progress for oxide based nanoparticles but for limited set of filler-matrix systems; not seen specifically for UF or mold compound

Need to avoid cracking in bending stresses with thin silicon, CTE between silicon and the flexible substrate and high adhesion to IC materials. Flow compatible with flip chip underfill to enable one step (UF and Mold).

Using nanoparticles, low CTEs can be achieved, but the viscosity goes up upon addition of nanoparticles and their dispersion is difficult to control at high loadings. In order to achieve high toughness [to withstand bending stress], filler-matrix adhesion needs to be strong (Improved Moisture Performance)

Control dispersion, dispensability of nanoparticle based composites at high loading; tailor filler-matrix interface to improve toughness (Improved Moisture Performance)

Some progress seen for oxide based nanoparticles but for limited set of filler-matrix systems; not seen specifically for UF or mold compound

3D Interconnects (Thermal & thermal Mechanical Stress need to be addressed especially for k ~<2)

High interfacial adhesion, high fracture toughness, low CTE (between Si and substrate CTE), resistance to electromigration, low process temperature, low moisture sensitivity, stress decoupling capacity

High current capacity with reliability in the use case with low assembly cost.

No delamination of layers in packaging structures in target use cases

Ultra high dielectric constant materials

Table ERM12 ITWG Earliest Potential ERM Insertion Opportunity Matrix


Application Ge

& II

I-V

Nan

owire

s

Gra

phen

e

Oxi

de N

anop

artic

les

Met

al N

anop

artic

les

Nov

el M

acro

mol

ecul

es

Self

Ass

embl

ed M

ater

ials

Com

plex

Met

al O

xide

s

Process Materials

Lithography

Device: Memory MRAM

Device: Logic

Interconnect

Packaging

LEGENDEarliest Potential Insertion Current Apps 3-5 yrs 5-10 yrs 10-15 yrs 15+ yrs Not on the Roadmap

Car

bon

Nan

otub

es a

nd

othe

r Met

al N

anot

ubes

Spin

Mat

eria

ls (F

e, C

o, M

n,

Ni,

etc.

)

tables focus b itrs

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