1 erd 2011 itrs summer conference – san francisco – july 13, 2011 itrs public conference...

1 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011

ITRS Public ConferenceEmerging Research Devices

Jim Hutchby – SRCJuly 13, 2011

2011 ERD Chapter

Work in Progress --- Not for Publication2 ERD WG 12/05/10 & 12/2/10

Hiroyugi Akinaga AIST Tetsuya Asai Hokkaido U. Yuji Awano Keio U. George Bourianoff Intel Michel Brillouet CEA/LETI Joe Brewer U. Florida John Carruthers PSU Ralph Cavin SRC An Chen GLFOUNDRIES U-In Chung Samsung Byung Jin Cho KAIST Sung Woong Chung Hynix Luigi Colombo TI Shamik Das Mitre Erik DeBenedictis SNL Simon Deleonibus LETI Bob Fontana IBM Paul Franzon NCSU Akira Fujiwara NTT Christian Gamrat CEA Mike Garner Intel Dan Hammerstrom PSU Wilfried Haensch IBM Tsuyoshi Hasegawa NIMS Shigenori Hayashi Matsushita Dan Herr SRC Toshiro Hiramoto U. Tokyo Matsuo Hidaka ISTEK Jim Hutchby SRC Adrian Ionescu EPFL Kiyoshi Kawabata Renesas Tech Seiichiro Kawamura Selete Suhwan Kim Seoul Nation U Hyoungjoon Kim Samsung

Atsuhiro Kinoshita Toshiba Dae-Hong Ko Yonsei U. Hiroshi Kotaki Sharp Mark Kryder INSIC Zoran Krivokapic GLOBALFOUNDRIES Kee-Won Kwon Seong Kyun Kwan U.Jong-Ho Lee Hanyang U. Lou Lome IDA Hiroshi Mizuta U. Southampton Matt Marinella SNL Kwok Ng SRC Fumiyuki Nihei NEC Ferdinand Peper NICT Yaw Obeng NIST Dave Roberts Nantero Barry Schechtman INSIC Sadas Shankar Intel Atsushi Shiota JSR Micro Satoshi Sugahara Tokyo Tech Shin-ichi Takagi U. Tokyo Ken Uchida Tokyo Inst. Tech. Thomas Vogelsang Rambus Yasuo Wada Toyo U. Rainer Waser RWTH A Franz Widdershoven NXP Jeff Welser NRI/IBM Philip Wong Stanford U. Dirk Wouters IMEC Kojiro Yagami Sony David Yeh SRC/TI Hiroaki Yoda Toshiba In-K Yoo SAIT Victor Zhirnov SRC

Emerging Research Devices Working Group

3 ERD2011 ITRS Summer Conference – San Francisco – July 13, 2011

year

Beyond CMOS

Elements

Existing technologies

New technologies

Evolution of Extended CMOS

More Than Moore

ERD-WG in Japan


Changed Scope of Emerging Research Devices Chapter

♦ New More-than-Moore Section added – Focused on RF ♦ Emerging Research Memory Devices section broadened

in 2011 to include: New “Storage Class Memory” Subsection New Memory “Select Device” Subsection

♦ Emerging Research Logic section changed Transitioned n-InGaAs & p-Ge alternate channel

MOSFETs to PIDS & FEP. Synchronized more closely with the Nanoelectronics

Research Initiative (NRI)♦ Expanded technology Benchmarking section♦ Expanded Architecture Section


2011 ERD Chapter Emerging Memory Devices Emerging Logic Devices More-than-Moore Devices Benchmarking and Assessing

Emerging Devices Emerging Architectures


Resistive Memories

2009 Memory Technology Entries

Redox Memory−Electrochemical memory−Valence change memory− Fuse/Antifuse (Thermochemical memory}Molecular Memory

Electronic Effects Memory− Charge trapping− Metal-Insulator Transition− FE barrier effects

Spin Transfer Torque MRAMNanoelectromechanical Nanowire PCMMacromolecular (Polymer)

Capacitive MemoryFeFET Memory


Resistive Memories

2011 Memory Technology Entries

Electronic Effects Memory− Charge trapping− Metal-Insulator Transition− FE barrier effects

Spin Transfer Torque MRAMNanoelectromechanical Nanowire PCMMacromolecular (Polymer)

Capacitive MemoryFeFET Memory

Redox Memory−Electrochemical memory−Valence change memory− Fuse/Antifuse (Thermochemical memory}Molecular Memory


ERD/ERM Memory Technology Assessment Workshop

ITRS ERD/ERM identified two emerging memory technologies for accelerated research & development:

1) STT-MRAM and 2) Redox Resistive RAM

Redox Memory Cell STT-Memory Cell


Memory Hierarchy – Future Memory Challenge

Al Fazio - IntelNVM cost/gigabyte ~ $1


One Diode – One Resistor (1D1R) Memory Cell

H-S. P. Wong – Stanford U.

Select Device = Diode


2009 Logic Technology Tables

Table 1 – Extending MOSFETs to the End

of the Roadmap _____________

CNT FETsGraphene nanoribbons

III-V Channel MOSFETsGe Channel MOSFETs

Nanowire FETsNon-conventional Geometry Devices

Table 2- UnconventionalFETS, Charge-based

Extended CMOS _______________

Tunnel FET I-MOS

Spin FET SET

NEMS switchNegative Cg MOSFET

Table 3 - Non-FET, Non Charge-based ‘Beyond

CMOS’ devices _______________

Collective Magnetic DevicesMoving domain wall devices

Atomic SwitchMolecular Switch

Pseudo-spintronic DevicesNanomagnetic (M:QCA)


2011 Logic Technology Tables

Table 1 – Extending MOSFETs to the End

of the Roadmap

___________

CNT FETsGraphene nanoribbons

III-V Channel MOSFETs

Ge Channel MOSFETsNanowire FETs

Tunnel FET Non-conventional Geometry Devices

Table 2- UnconventionalFETS, Charge-based

Extended CMOS Devices

_______________

Spin FET& Spin MOSFETNegative Cg MOSFET

NEMS switchExcitonic FET

Mott FETTunnel FET

I-MOSSET

Table 3 - Non-FET, Non Charge-based ‘Beyond

CMOS’ Devices

_______________

Spin Transfer Torque LogicMoving domain wall devicesPseudo-spintronic DevicesNanomagnetic (M:QCA)Negative Cg MOSFET

All Spin Logic Molecular Switch

Atomic SwitchBiSFET


ERD/ERM Logic Technology Recommended Focus:Carbon-based Nanoelectronics – Carbon Nanotubes and Graphene

Conventional Devices

Cheianov et al. Science (07)

Graphene Veselago lense

FETBand gap engineered Graphene nanoribbons

Nonconventional Devices

Trauzettel et al. Nature Phys. (07)

Graphene pseudospintronics

Son et al. Nature (07)

Graphene Spintronics

Graphene quantum dot

(Manchester group)

P. Kim – Columbia U.

17 ERD2011 ITRS Summer Conference – San Francisco – July 13, 2011 17

Wireless underlying architecture / functions

LNA

LO

ADC

PA DAC

LO

spin-torque oscillator

nanoradioIntermediate level

function

Lower level functions

NEMS nanoresonator

filter oscillator mixer

graphene

011001010…

control

rf wave

Higher level function


All 3 metrics responding consistently – energy and area superiority.Little change in the energy delay product.

1.00E-02

1.00E-01

1.00E+00

1.00E+01

1.00E+02

DELAY ENERGY AREA

INV

NAND2

ADD32

Preferred

Corner Preferred

CornerPreferred

Corner

ENERGY

DELAY AREA

BenchmarkingNRI Median Switch Characteristics


Four Architectural Projections

1) Hardware Accelerators execute selected functions faster than software performing it on the CPU.

2) Alternative switches often exhibit emergent, idiosyncratic behavior. They also maybe non-volatile. We should exploit them.

3) CMOS is not going away anytime soon.

4) New switches may improve high utilization accelerators


Matching Logic Functions & New Switch Behaviors

Single Spin

Spin Domain

Tunnel-FETs

NEMS

MQCA

Molecular

Bio-inspired

CMOL

Excitonics

?

Popular Accelerators New Switch Ideas

Encrypt / Decrypt

Compr / Decompr

Reg. Expression Scan

Discrete COS Trnsfrm

Bit Serial Operations

H.264 Std Filtering

DSP, A/D, D/A

Viterbi Algorithms

Image, Graphics

Example: Cryptography Hardware AccelerationOperations required: Rotate, Byte Alignment, EXORs, Multiply, Table LookupCircuits used in Accel: Transmission Gates (“T-Gates”)New Switch Opportunity: A number of new switches (i.e. T-FETs) don’t have

thermionic barriers: won’t suffer from CMOS Pass-gate VT drop, Body Effect, or Source-Follower delay.

Potential Opportunity: Replace 4 T-Gate MOSFETs with 1 low power switch.


ERD – Key Messages

♦ New More-than-Moore Section added – Focused on RF devices♦ Emerging Research Memory Devices section broadened in 2011

to include: New “Storage Class Memory” Subsection New Memory “Select Device” Subsection Transitioned STT-MRAM to PIDS & FEP Introduced new memory device category – Redox RAM

♦ Emerging Research Logic changes: Transitioned n-InGaAs & p-Ge alternate channel MOSFETs

to PIDS & FEP. Synchronized more closely with the Nanoelectronics

Research Initiative (NRI)♦ Expanded technology benchmarking section♦ Expanded Architecture Section

1 erd 2011 itrs summer conference – san francisco – july 13, 2011 itrs public conference...

Documents

molecular memory slide

emerging memory technologies

erd chapter slide

erd wg

cmos devices

moore erdwg

diode slide

group slide