itrs past, present and future - solid state...

May, 2015 P.GarginiConFab

Paolo GarginiPaolo Gargini Chairman ITRSChairman ITRS

Fellow IEEE, Fellow IFellow IEEE, Fellow I--JSAPJSAP

ITRSPast, Present and

Future

AgendaAgenda��

In the beginningIn the beginning��

Geometrical ScalingGeometrical Scaling��

ITRS 1.0ITRS 1.0��

Equivalent ScalingEquivalent Scaling��

Post CMOSPost CMOS��

3D Power Scaling3D Power Scaling��

Heterogeneous IntegrationHeterogeneous Integration

May, 2015 P.GarginiConFab 3

The First Planar Integrated Circuit The First Planar Integrated Circuit ~1961~1961

Integrated Circuits Economics

Gordon Moore at Fairchild Semiconductors

MooreMoore’’s Law s Law -- 19651965

2X/Year ~65,000

With unit cost falling as the number of components per circuit rises, by 1975 economics may dictate squeezing as many as 65,000 components on a single silicon chip

What could you do with 65,000 components?

Gordon Moore

April 19, 1965

Question

ENIAC (Electronic Numerical Integrator and Computer)

ENIAC weighted 30 tons and occupied 1500 squared feet of space.

CustomComponents

SemiconductorCompany

Standard Components

The Semiconductor Business in the 70sSystem DesignerProprietary

ProductDefinition

SystemIntegration

ProductDefinition

OpenMarket

The story of the struggle between Fairchild Instruments and Texas Instruments for the contract to supply the integrated circuitry for Polaroid's SX-70 camera,

introduced in 1972, is related. Research and development work by both companies is described. The problems caused by Polaroid's secrecy regarding

the overall camera design are highlighted

The SX-70

IEEE Spectrum archiveVolume 26 Issue 5, May 1989

First Age of Scaling(Self-aligned Silicon Gate)

Phase 1

Substrate

Source Drain

Basic MOS Device(1968-2003)

MOS Transistor ScalingMOS Transistor Scaling (1972)(1972)

ParameterSupply Voltage (Vdd)

Channel Length (Lg, Le)Channel Width (W)

Gate Oxide Thickness (Tox)Substrate Doping (N)

Drive Current (Id)

Gate Capacitance (Cg)

Gate Delay Active Power

ScaledVoltage

ConstantVoltage

1/s 1/s

* Does Not Include Carrier Velocity Saturation

R. H. Dennard et Others, “Design of Micron MOS Switching Devices”, IEDM, 1972

MOS Transistor MOS Transistor ScalingScaling (1970s)(1970s)

S=0.7[0.5x per 2 nodes]

Pitch Gate

MooreMoore’’s Law and Dennards Law and Dennard’’s s Scaling Laws ConvergenceScaling Laws Convergence

50% AREA READUCIONGENERATION TO GENERATION

=> 30% LINEAR FEATURE REDUCTION

0.5 = 0.7

Memory Cell Evolution

International Electron Device Meeting, December 1975

Second Update of Moore’s Law

101112

141516

191817

2X/Year

2X/2Year

IC Industry at a GlanceIC Industry at a Glance (1975)(1975)

Driver Cost/transistor -> 50% Reduction

How 2x Density/2 years (Moore)

Method Geometrical Scaling (Dennard)

1948 1955 1957 1968 1973

Let’s Have a Start up!

The Computer Hobbyists

IBM Total Solution

August 12, 1981

Operating system IBM BASIC / PC DOS 1.0CP/M-86UCSD p-SystemCPU Intel 8088 @ 4.77 MHzMemory 16 kB ~ 256 kBSound 1-channel PWM

First Moore’s Law Acceleration

1970 1980 2000

2X/1Y 4X/3Y

DRAMMPUEPROMFLASH 1FLASH 2

Over 40 years of Moore’s LawOver 40 years of Moore’s Law

Wintel

Windows

Product Definition

Product Design

SemiconductorCompany

Standard Components

Open Market

SystemIntegration

The Semiconductor Business in the 80-90s

WintelProprietary

SoftwareOS and Apps

StandardComponents

W/Al/CuWVia studs

oxide; air; polyimide; low dielectricoxideInterleveldielectric

Al, Cu ( thick) Al basedWires

planarInterconnect

same + raised S/DLDD*/MDD ‡; S/D

Source/drain

n; n/p poly; poly/ silicideGate electrode

thermal/rapid thermal oxidationthermalGate oxide

STI †/SOILOCOS/STI †/SOI

Isolation

20100.07 µm

20070.10 µm

20040.13 µm

20010.18 µm

19980.25 µm1995

0.35 µm

1994 NTRS

Gate Dielectric ScalingGate Dielectric Scaling

4 8 12

Monolayers

1997 NTRS

You Are Here!

Silicon substrate

1.2nm SiO2

From My Files

Tutorial for SEMI P.Gargini

1998 ITRS Update

• Participation extended to: EECA, EIAJ, KSIA, TSIA at WSC on April 23,1998

• 1st Meeting held on July 10/11,1998 in San Francisco

• 2nd meeting held on December 10/11,1998 at SFO• 50% of tables in 1997 NTRS required some changes• 1998 ITRS Update posted on web in April 1999

CMOS Future DirectionsCMOS Future Directions70%/2-3year

70% / 2-3yearEquivalent Scaling2005-2014

??/2-3year

2X Performance/2-3yearIntegrated Solutions2000-2014

New Devices2010-20XX

1970-2004

Traditional ScalingFeatures

ITRS 7/11/1998

From My Files

SOC, SIP,3D

Nanotech

More Moore

ITRS 7/11/1998

Second Age of Scaling(Equivalent Scaling)

Phase 2

ITRS 1.0

The Ideal MOS TransistorThe Ideal MOS Transistor

From My Files

Fully SurroundingMetal Electrode

High-KGate Insulator

Fully Enclosed,DepletedSemiconductor

Low ResistanceSource/Drain

DrainSourceMetal Gate Insulator

Band EngineeredSemiconductor

Equivalent ScalingEquivalent Scaling

��

Strained SiliconStrained Silicon��

HighHigh--K/Metal GateK/Metal Gate

��

MultiMulti--gategate��

Higher PerformanceHigher Performance

IC Industry at a GlanceIC Industry at a Glance From Geometrical to Equivalent ScalingFrom Geometrical to Equivalent Scaling

(1998(1998-->2003)>2003)

Driver Cost/transistor-> 50% Reduction

Method Equivalent Scaling (ITRS1.0)

High-k/Metal-Gate(year 2000)

Mobility InnovationMobility Innovation

SiGeSiGe

Strained Strained PP--Channel Channel TransistorTransistor

High Stress Film

Strained Strained NN--Channel Channel TransistorTransistor

Source: Intel

May, 2015 P.GarginiConFabIntelIntel

0.2 0.4 0.6 0.8 1.0 1.2ION (mA/um)

(nA/um)

PMOS NMOS

90 nm20022004

65 nm 2004

Improved Transistor Performance

65 nm transistors increase drive current 10-15% with enhanced strain

May, 2015 P.GarginiConFab2008 ISS US 44

Gate Oxide LeakageGate Oxide Leakage

Gate oxide scaling stopped due to leakage

(relative.)

Technology Generation

Gate Leakage

PhysicalTox (nm)

May, 2015 P.GarginiConFab 452007 4545

May, 2015 P.GarginiConFab2008 ISS US 46

Gate Oxide LeakageGate Oxide Leakage

(relative.)

Technology Generation

Gate Leakage

PhysicalTox (nm)

High-k dielectric breaks through this barrier

May, 2015 P.GarginiConFabTransistor Scailing / Tahir Ghani

HighHigh--k+Metalk+Metal Gate Gate Performance / Power BenefitsPerformance / Power Benefits

Transistor Performance vs. S/D LeakageTransistor Performance vs. S/D Leakage

Transistor Drive Current (rel.)

>5x Lower Leakage

>20%Higher Drive

65 nm 45 nm

0.5 1.0 1.5

Leakage Current(nA/um)

Source: Intel Internal

25% Idsat gain demonstrated for 45nm CMOS vs. 65nm CMOS at fixed Ioff

SourceDrain

Source

Si fin - Body!

FinFET

Surrounding the SemiconductorSurrounding the Semiconductor

Source

Tri-Gate

22 nm Tri-Gate Transistor

Gates Fins

Mark Bohr, Kaizad Mistry, May 2011 4949

Incubation TimeIncubation Time��

Strained SiliconStrained Silicon•• 19921992-->>20032003

��

HKMGHKMG•• 19961996-->2007>2007

��

Raised S/DRaised S/D•• 19931993-->2009>2009

��

MultiGatesMultiGates•• 19971997-->2011>2011 ~ 12-15 years

NRI Funded UniversitiesNRI Funded Universities Finding the Next Switch Finding the Next Switch

UC Los AngelesC BerkeleyUC IrvineUC Sana BarbaraStanfordU DenverPortland StateU Iowa

Notre Dame PurdueIllinois-UC Penn StateMichigan UT-DallasCornell GIT

UT-Austin Rice Texas A&MUT-Dallas ASU Notre DameU. Maryland NCSU Illinois UC

ColumbiaHarvardPurdueUVAYaleUC Santa BarbaraStanfordNotre DameU. Nebraska/LincolnU. MarylandCornellIllinois UCCaltechUC BerkeleyMITNorthwesternBrownU Alabama

SUNY-Albany GIT HarvardPurdue RPI ColumbiaCaltech MIT NCSUYale UVA

Over 30 Universities in 20 States

TUNNEL FET

GRAPHENESPIN LOGIC

GRAPHENE

Dec 2010

STARnet Program LaunchedSTARnet Program Launched 20152015

MISSION: Long-term breakthrough research that results in paradigm shifts and multiple technology options. Focused on beyond CMOS technology options and systems integration and discovery to enable both CMOS and beyond CMOS components.

Collaborative network of six multi-university centers involving 39 U.S. universities

$194 million over 5 years from industry and DARPA�

Supports 145 research faculty and 400 graduate students�

Member companies from semiconductor and defense industry

GLOBALFOUNDRIES�

IBM�

Intel Corporation

Micron Technology�

Raytheon�

Texas Instruments�

United Technologies

http://www.src.org/program/starnet/

NRI Nanoelectronics Research Initiative

"Future generations of electronics will be based on new devices and circuit architectures, operating on physical principles

that cannot be exploited by conventional transistors. NRI seeks the next device that will propel computing

beyond the limitations of current technology."

NRI Mission and DescriptionProgram Mission

Demonstrate non-conventional, low-energy technologies which can outperform CMOS on critical applications in ten years and beyond.

Intermission

22 nm Tri-Gate Transistor

Gates Fins

Mark Bohr, Kaizad Mistry, May 2011 5959

How many more technology generationscan

Equivalent Scaling be extended for ?

Question

Multigate FET Offers a Simple Way for Scaling and Improving Performance

Semicon Japan, December 6, 2013

May, 2015 P.GarginiConFabMark Bohr, August 11, 2014

Second Moore’s Law Acceleration

May, 2015 P.GarginiConFabMark Bohr, August 11, 2014

2017 2015 2013

2013 ITRS6767

Technology Node ScalingTechnology Node ScalingToday’s Challenge

Apr 19th 2015

Third Age of Scaling(3D Power Scaling)

Phase 3

Vertical Memory Architecture

May, 2015 P.GarginiConFabKinam Kim, ISSCC, Feb 23, 2015

Toshiba Develops World's First 48-Layer BiCS (Three Dimensional Stacked Structure Flash Memory)

Toshiba, and sample shipments of the 3D structure adopted NAND-type flash memory of 48-layer

Date March 27, 2015 Toshiba has announced that the 26th, began sample shipments of NAND-type flash memory that employs a three-dimensional (3D) structure of stacking the storage element vertically. First of the 3D flash memory for the company. At 48 the number of influences layer performance, it exceeded the existing products of competing Korea Samsung Electronics (32 layers). Compared to existing planar structure product, and appeal to the point of excellent writing speed and reliability of data to be proposed, such as enterprise data centers (DC). (Nobuyuki Goto)

3D NAND

Vertical Logic Architecture

IC Industry at a GlanceIC Industry at a Glance From Equivalent to 3D Power Scaling From Equivalent to 3D Power Scaling

(2015(2015-->2021)>2021)

Driver Cost/transistor & power reduction

Method 3D Power Scaling (ITRS2.0)

but the World has changed under are very own eyes

MM+MtMMM+MtM=Heterogeneous Integration=Heterogeneous Integration2006

More than Moore: Diversification

Combining SoC and SiP: Heterogeneous IntegrationBas

BiochipsSensorsActuators

HVPowerAnalog/RF Passives

16 nm...V

Information Processing

Digital contentSystem-on-chip

Beyond CMOS

Interacting with people and environment

Non-digital contentSystem-in-package

Customized Functionality

20078585

TabletApril 2010

A WiFi-only model of the tablet was released in April 2010, and a WiFi+3G model was introduced about a month later

1991 Micro Tech 2000Workshop Report

1994NTRS1992NTRS 1997NTRS

21th Anniversary of TRS

Japan KoreaEurope Taiwan USA

http://www.itrs.net

2001 ITRS1999 ITRS1998 ITRSUpdate

2000 ITRSUpdate

2002 ITRSUpdate

2004 ITRSUpdate

2006 ITRSUpdate2003 ITRS 2005 ITRS 2007 ITRS

2008 ITRSUpdate

2010 ITRSUpdate2009 ITRS 2012 ITRS

Update2011 ITRS

2013 ITRS

The Last ITRS 1.0

2013 ITRS ITWGs2013 ITRS ITWGs1.1. System DriversSystem Drivers2.2. DesignDesign3.3. Test & Test EquipmentTest & Test Equipment4.4. Process Integration, Devices, & StructuresProcess Integration, Devices, & Structures5.5. RF and A/MS Technologies RF and A/MS Technologies 6.6. Emerging Research DevicesEmerging Research Devices7.7. Emerging Research MaterialsEmerging Research Materials8.8. Front End ProcessesFront End Processes9.9. LithographyLithography10.10. InterconnectInterconnect11.11. Factory IntegrationFactory Integration12.12. Assembly & PackagingAssembly & Packaging13.13. Environment, Safety, & HealthEnvironment, Safety, & Health14.14. Yield EnhancementYield Enhancement15.15. MetrologyMetrology16.16. Modeling & SimulationModeling & Simulation17.17. MEMsMEMs

Restructuring the ITRS to represent the New Ecosystem

More Moore Beyond Moore

More than Moore

Heterogeneous Integration

System Integration

Customized FunctionalityOP

SYSTEM

APPLETS

Outside System Connectivity

Beyond 2020

ITRS 2012

ITRS 2.0

Beyond 2020Beyond 2020

Outside System Connectivity Outside System Connectivity

System Integration System Integration

Heterogeneous Integration Heterogeneous Integration

Beyond Moore Beyond CMOS

More than Moore Heterogeneous Components

More Moore More Moore

Manufacturing Factory Integration

Themes Focus TeamsApril 2014

Increasing Degree of IntegrationIncreasing Degree of Integration

Qualcomm Snapdragon TM Family

Inside the Apple A7 from the iPhone 5s(Courtesy of Chipworks)

1 billion transistors on a die 102 mm2

Example of Segregating: Sensor HubExample of Segregating: Sensor Hub• To monitor user behavior, sensors must be always-on• Power penalty is high for main processor• Reverse trend against integration

• (WAS) Main processor controls sensors directly• (IS) Low power sensor hub coprocessor controls sensors

instead(WAS) (IS)

iPhone 6

A 8 (2 Billion Transistors)

The Apple A8 is, of course, the most interesting element in the new iPhone 6. All clues point to it being manufactured by TSMC on a 20nm node, and that makes it one of the first 20nm chips out there. The A8 is also some 13% smaller than last year’s A7, while packing nearly double the amount of transistors - up from around 1 billion to some 2 billion transistors in the Apple A8. And yes, RAM is still 1GB on the iPhone 6. 100100

Leakage and Power Reduction

102102

Rebooting Computing: Rebooting Computing: Rethinking All Levels of Rethinking All Levels of

How We Compute How We Compute Tom ConteTom Conte

Professor of ECE & CSProfessor of ECE & CSGeorgia Institute of TechnologyGeorgia Institute of Technology

2015 President, Computer Society2015 President, Computer Society

IEEE Rebooting ComputingIEEE Rebooting Computing

104104

Why IEEE? PreWhy IEEE? Pre--competitvecompetitve, Inclusive, Worldwide, Inclusive, Worldwide

Council on Electronic Design Automation

Circuits & Systems Society

IEEE Rebooting Computing

Goal: Rethink Everything: Turing & Von Neumann to now

105105

Q: How do we get back to Q: How do we get back to exponential performance scaling?exponential performance scaling?

IEEE Rebooting Computing InitiativeIEEE Rebooting Computing Initiative

106106

With unit cost falling as the number of components percircuit rises, by 1975 economics may dictate squeezing asmany as 65,000 components on a single silicon chip

What could you do with 65,000 components?

Gordon Moore

April 19, 1965

With unit cost falling as the number of components percircuit rises, by 2015 economics may dictate squeezing asmany as 6,500,000,000 components on a single silicon chip

What could you do with 6,500,000,000 components?

Paolo Gargini

February 26, 2015

Recurring Questions

109109

Figure MEMS Sensors trends for “Wearable” technologies – The MEMS TWG has adopted this application as a case study for More

than Moore roadmapping.

Inside the Apple WatchInside the Apple Watch

[source] https://www.abiresearch.com/press/apple-watch-insides-pcb-details- revealed-for-the-f/

113113

Figure MEMS illustrates the many inertial sensors used in a fully featured car today. In some cases, there are up to 15 axes of inertial sensors (accelerometer and gyro) used. As there are only six possible degrees of mechanical freedom, it is obvious that many of these sensors are redundant. We have arrived at this situation because historically each system has been purchased from different suppliers. But today

the concept of a cluster of inertial sensors sending their information to whatever system needs it is becoming the goal of many automotive OEMs. Can you say “Plug and Play”?

ConclusionsConclusions��

““Geometrical ScalingGeometrical Scaling”” led the IC Industry for 3 decadesled the IC Industry for 3 decades

Cooperative and distributed research and manufacturing methods Cooperative and distributed research and manufacturing methods highlighted by highlighted by ITRS ITRS emerged as cost effective means of reducing costs emerged as cost effective means of reducing costs since the midsince the mid--90s90s

��

FCRP, NRI, Sematech, IMEC and Government organizations actively FCRP, NRI, Sematech, IMEC and Government organizations actively cooperated in cooperated in advanced researchadvanced research

��

““Equivalent ScalingEquivalent Scaling”” saved the Semiconductor Industry since saved the Semiconductor Industry since the beginning of the previous decadethe beginning of the previous decade

��

Preliminary evaluation of postPreliminary evaluation of post--CMOS candidates published in 2010CMOS candidates published in 2010

““3D Power Scaling3D Power Scaling”” is the next phase of (accelerated) is the next phase of (accelerated) scalingscaling

��

Post CMOS devices and emerging architectures are being Post CMOS devices and emerging architectures are being jointly evaluatedjointly evaluated-->ITRS/RC>ITRS/RC

117117

itrs past, present and future - solid state...

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