analog-to-dii cigital converterskxc104/class/cse577/11s/lec/s08adc.pdfanalog-to-dii cigital...
TRANSCRIPT
![Page 1: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/1.jpg)
CSE 577 Spring 2011
A i i CAnalog-to-Digital Converters
Jaehyun Lim, Kyusun Choi
D t t f C t S i d E i iDepartment of Computer Science and EngineeringThe Pennsylvania State University
Mixed Signal Chip Design Lab
![Page 2: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/2.jpg)
ADC Glossary
DNL (differential nonlinearity)- measure of the maximum deviation from the ideal
step size of 1 LSB
Mixed Signal Chip Design Lab
![Page 3: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/3.jpg)
ADC Glossary
INL (integral nonlinearity)- deviation of the entire transfer function from the
ideal function
Mixed Signal Chip Design Lab
![Page 4: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/4.jpg)
ADC Glossary
Offset Error- difference between the ideal LSB transition to the
actual transition point
Mixed Signal Chip Design Lab
![Page 5: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/5.jpg)
ADC Glossary
Gain Error- how well the slope of the actual transfer function
matches the slope of the ideal transfer function
Mixed Signal Chip Design Lab
![Page 6: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/6.jpg)
ADC Glossary
Resolutionf- number of discrete values it can produce
Monotonic- digital output code always increases as the ADCdigital output code always increases as the ADC
analog input increasesFull scale
lt ADC t- voltage range ADC can acceptAliasing- due to unwanted signals beyond the Nyquist limitdue to unwanted signals beyond the Nyquist limit- to prevent, all undesired signals must be filtered
Mixed Signal Chip Design Lab
![Page 7: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/7.jpg)
ADC Glossary
SINAD (signal-to-noise and distortion)RMS l f th t t i l t th RMS l- RMS value of the output signal to the RMS value of all of the other spectral components below half the clock frequency
ENOB (effective number of bits)- dynamic performance of an ADC at a specificdynamic performance of an ADC at a specific
input frequency and sampling rate
761SINAD02.6
76.1−=
SINADENOB
Mixed Signal Chip Design Lab
![Page 8: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/8.jpg)
High Speed ADC Architecture
Flash ADC
- highest speed
large # of comparators- large # of comparators
- large size
- large power consumption
8 bit i l ti- 8-bit maximum resolution
Mixed Signal Chip Design Lab
![Page 9: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/9.jpg)
High Speed ADC Architecture
Two-Step Flash ADC
- SHA
- D/A converter
- subtractor
- coarse flash ADC (MSB)coarse flash ADC (MSB)
- find flash ADC (LSB)
- reduce # of comparatorsreduce # of comparators
2N-1 2(2N/2-1)
Mixed Signal Chip Design Lab
![Page 10: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/10.jpg)
High Speed ADC Architecture
Pipelined ADC
- multi-stage conversion
hi h d- high speed
- acceptable power
- each stage has SHA, ADC, DAC, subtractor, Amp
- different conversion step concurrently
Mixed Signal Chip Design Lab
![Page 11: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/11.jpg)
High Speed ADC Architecture
Folding ADC
- no SHA (flash)
- reduce # of comparatorsreduce # of comparators
(two step flash)
ll hi h d- small area, high speed
- rounding problem
Mixed Signal Chip Design Lab
![Page 12: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/12.jpg)
High Speed ADC Architecture
Time-Interleaved ADC
- multiple ADCs in parallel high speed
- offset/gain mismatchg
- phase skew
Mixed Signal Chip Design Lab
![Page 13: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/13.jpg)
And More ADC Architectures
Algorithmic ADC
- low power, small size, slow
Integrating-Type ADCg g yp
- high accuracy, simple architecture, very slow
S i A i ti ADCSuccessive Approximation ADC
R&C / C&R Type ADC
Interpolating ADC
Mixed Signal Chip Design Lab
![Page 14: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/14.jpg)
Design Consideration – Flash ADC
Large Input Capacitance• parallel structure of 2N-1 comparators• limits speed performance• large size buffer
Bubble / Sparkle• no SHA, comparator mismatch…• error in thermometer code• error in thermometer code• solution : 3-input NAND
Mixed Signal Chip Design Lab
![Page 15: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/15.jpg)
Design Consideration – Flash ADC
Metastability• input to ADC ≈comparator reference• indeterminate output error• solution : latch pipelining (extra gain)
gray encoding (no signal split)
Mixed Signal Chip Design Lab
![Page 16: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/16.jpg)
Design Consideration – Flash ADC
Clock Distribution and Timing• clock travels long distance on a large ADC chip• different delay, different loading
Kickback NoiseKickback Noise• disturbs reference
Mixed Signal Chip Design Lab
![Page 17: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/17.jpg)
Design Consideration – Two-Step Flash ADC
Subtractor Gain• without gain stage
– output of subtractor = 1-LSB of coarse ADC– difficult comparator design
(offset < 1-LSB of fine ADC)• with gain stage
delay– delay– mismatch between subtractor output and fine
ADC input full scalepmissing code / nonmonotonicity
Mixed Signal Chip Design Lab
![Page 18: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/18.jpg)
Design Consideration – Two-Step Flash ADC
Nonlinearity
residue residue
V
residue
V
residue
including errors- gain mismatch
DNL INL
SHA
Vin Vin- DNL, INL- offset- ...
SHAanaloginput
level sensed by subtractor
t
level digitized by coarse ADC
level sensed by subtractor
t1 t2
ΔV
Mixed Signal Chip Design Lab
t1 t2
![Page 19: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/19.jpg)
Design Consideration – Pipelined Flash ADC
MDAC (Multiplying D/A Converter)- performs subtractor, gain amplifier, S/H, and DAC
Mixed Signal Chip Design Lab
![Page 20: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/20.jpg)
Design Consideration – Pipelined Flash ADC
MDAC Operation removes offset
Vx
(2N-1)·C·Vin + C·VinQi =
2N C V= 2N·C·Vin
Mixed Signal Chip Design Lab
![Page 21: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/21.jpg)
Design Consideration – Pipelined Flash ADC
MDAC Operation
Qf = 2N·C·DVref + C·VQf 2 C DVref + C Vo
from Qin=Qf, Vo = 2N(Vin-DVref)
Mixed Signal Chip Design Lab
![Page 22: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/22.jpg)
Design Consideration – Folding ADC
Rounding Problem- only linear at zero-crossings
limits resolution to ~10 bitslimits resolution to ~10 bits
Mixed Signal Chip Design Lab
![Page 23: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/23.jpg)
Design Consideration – Folding ADC
Multiple Folds
Mixed Signal Chip Design Lab
![Page 24: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/24.jpg)
Two-Step Flash ADC Implementation
SHA
4-bit Coarse ADC
3-bit Fine ADC
Resistor-String DAC
Voltage Subtractor
Amplifier
Registers
Mixed Signal Chip Design Lab
![Page 25: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/25.jpg)
Two-Step Flash ADC Implementation
Coarse ADC
Fat-Tree EncoderBubble Correction
Mixed Signal Chip Design Lab
Bubble Correction
![Page 26: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/26.jpg)
Two-Step Flash ADC Implementation
Coarse ADC
Mixed Signal Chip Design Lab
![Page 27: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/27.jpg)
Two-Step Flash ADC Implementation
Resistor-String DAC
• voltage scaling DAC
• simple
• fast
• small (under 8-bit)
• resistor mismatchingresistor mismatching
Mixed Signal Chip Design Lab
![Page 28: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/28.jpg)
Two-Step Flash ADC Implementation
Resistor-String DAC
00011111
Mixed Signal Chip Design Lab
![Page 29: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/29.jpg)
Two-Step Flash ADC Implementation
SHA
input
outputoutput
Mixed Signal Chip Design Lab
![Page 30: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/30.jpg)
Two-Step Flash ADC Implementation
Voltage Subtractor
V2
V1 8 x (V1-V2)
Mixed Signal Chip Design Lab
![Page 31: Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage](https://reader033.vdocuments.net/reader033/viewer/2022042005/5e6f5e30640d7030a94bdc8d/html5/thumbnails/31.jpg)
Two-Step Flash ADC Implementation
Things To Be Done
• voltage subtractor and gain amplifiervoltage subtractor and gain amplifier
- input voltage range for the subtractor
- output offset
- proper gain setting (input range of fine ADC)
• 3-bit fine ADC
id ti l t th 4 bit ADC- identical to the 4-bit coarse ADC
Mixed Signal Chip Design Lab