CBP 2002Repository1 Overview PC Structure 1. CBP 2002Repository2

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<ul><li>Slide 1</li></ul> <p>CBP 2002Repository1 Overview PC Structure 1 Slide 2 CBP 2002Repository2 Slide 3 CBP 2002Repository3 CPU Caches System Bus Memory I/O controllers bridges Disk, Mouse Displays Keyboards Ethernet I/O Buses Slide 4 CBP 2002Repository4 caclulator Slide 5 CBP 2002Repository5 Stonehenge Slide 6 CBP 2002Repository6 Slide 7 CBP 2002Repository7 Sam 4 Series Master Data Memory Code Memory ALU r1 r2 r0 X Y W XY W 0 1 7 mar mdr Slide 8 CBP 2002Repository8 Sam 4 Series Master Data Memory Code Memory ALU r1 r2 r0 X Y W XY W 0 1 7 mar mdr Slide 9 CBP 2002Repository9 Sam 4 Bits Data Memory Code Memory ALU r1 r2 r0 X Y W XY W 0 1 7 mar mdr Slide 10 CBP 2002Repository10 Computer Clipart Slide 11 CBP 2002Repository11 Sam 4 outline Slide 12 CBP 2002Repository12 Memory CPU Arithmetic Logic Unit (ALU) CPU Control Unit Input Output Slide 13 CBP 2002Repository13 Data Memory 0 1 7 mar mdr X Y W Y W r1 r2 r0 X PC Code Memory Sam4 Bits X Y W Y W r1 r2 r0 X 0 1 7 mar mdr Slide 14 CBP 2002Repository14 Data Memory 0 1 7 mar mdr X Y W Y W r1 r2 r0 X PC Code Memory Sam4 Bits X Y W Y W r1 r2 r0 X 0 1 7 mar mdr Slide 15 CBP 2002Repository15 Memory Cells Slide 16 CBP 2002Repository16 Mem reg and inst for Sam 7 696 2315 1154 1453 2 1 0 231r3 unusedrtrsrdldr opcode destination Source regs Slide 17 CBP 2002Repository17 Spreadsheet Bits Slide 18 CBP 2002Repository18 Timing diag bits 1 T1T2T3T4T5 FetchDecode, Reg Op ALU OpMem Access Reg Write Slide 19 CBP 2002Repository19 Timing Diag Worksheet T1T2T3T4T5 FetchDecode, Reg Op ALU OpMem Access Reg Write Slide 20 CBP 2002Repository20 Timing diag bits 1 T1T2T3T4T5 Fetch Decode, Reg Op ALU Op Mem Access Reg Write T1T2T3T4T5 Fetch Decode, Reg Op ALU Op Mem Access Reg Write T1T2T3T4T5 Fetch Decode, Reg Op ALU Op Mem Access Reg Write T1T2T3T4T5 Fetch Decode, Reg Op ALU Op Mem Access Reg Write Slide 21 CBP 2002Repository21 Reg and ALU Bits (nonsam) Memory Register ALU r0 r1 r2 r3 r11 r0 ALU Slide 22 CBP 2002Repository22 More Reg ALU Bits (nonsam).. 0 8 16 24 32.. Slide 23 CBP 2002Repository23 MEM CPU DISK IO MEM CPU DISK IO Slide 24 CBP 2002Repository24 Turing Machine Bits S0 R Slide 25 CBP 2002Repository25 Logic gates Slide 26 CBP 2002Repository26 Buses Correctly Sized Components ! Slide 27 CBP 2002Repository27 Buses Correctly Sized Components ! Slide 28 CBP 2002Repository28 This Time ALU Mem Reg MemReg ALU Mem Reg MemReg Slide 29 CBP 2002Repository29 This Time ALU Mem Reg MemReg Slide 30 CBP 2002Repository30 coffee Slide 31 CBP 2002Repository31 Slide 32 CBP 2002Repository32 Pipeline template Slide 33 CBP 2002Repository33 Pipeline template Slide 34 CBP 2002Repository34 Pipeline template Slide 35 CBP 2002Repository35 Slide 36 CBP 2002Repository36 Slide 37 CBP 2002Repository37 Pipeline template Slide 38 CBP 2002Repository38 Performance incl. Stalls 5 cycles gives 5 loads so we have 1 cycle per load (CPL = 1) Speedup = 5. This is of course just the pipeline depth. (Assuming there are no stalls). Slide 39 CBP 2002Repository39 Increasing Shirt Throughput idle running idle running A. Wash then Dry B. Wash then Dry and Reload Wash time Slide 40 CBP 2002Repository40 blank Slide 41 CBP 2002Repository41 T1T2T3T4T5 FetchDecode, Reg Op ALU OpMem Access Reg Write Slide 42 CBP 2002Repository42 T1T2T3T4T5 Fetch Decode, Reg Op ALU Op Mem Access Reg Write Slide 43 CBP 2002Repository43 T1T2T3T4T5 Fetch Decode, Reg Op ALU Op Mem Access Reg Write </p>