iTOP LEPS Beam Test Analysis

LYNN WOOD

JULY 17, 2013PACIFIC NORTHWEST NATIONAL LABORATORY

Topics

LEPS Beam Test Summary

iTOP Electronics OverviewIRS3B ASIC

CorrectionsVoltageTiming

Current Analysistopcaf (software)Results

Next Steps

LEPS Beam Test – June 4-20, 2013

Goal: end-to-end test withFull quartz bar including mirror and prismFull bar of PMTs and ASIC-based electronicsBelle II DAQ-based readout (COPPER)

Facility: LEPS beamline at SPring-82 GeV photon beams generated by backward Compton scattering of UV laser photons off 8 GeV synchrotron ring electronsPhotons strike Pb target, produce e+/e- pairs that pass through detector

LEPS Configuration

e+ beam trigger from four countersg rate: 30 kHzTrigger rate: 10 HzDAQ rate: 5 Hz

Timing available from acceleratortiming signals: ~24.3 ps

Data taken at multiple angles of incidence and locations:

Cos q = 0 (normal to bar)Cos q = 0.39, x = 0cmCos q = 0.37, x = 20cm

iTOP Electronics Overview

Physical Layout

One SCROD

One ASIC

One carrier board

ASIC Block Diagram

Per channel:Single input128 sampling cells (capacitors)256 transfer cells32768 storage cells64 counters for digitization

Per ASIC:Timing generatorRamp generator (for digitization)

Uncertainties

In the ASIC:Voltage uncertainties

Comparator response (32768 x 8 per channel)ADC counter rates (64 per channel)Response of sampling array (128 x 8 per channel)

Possible difference in DC vs. AC responseInput coupling and signal frequency content

Timing uncertaintiesOverconstrained timing – overlap/gap between recordsVarying delays from sample-to-sampleBias voltage (and noise on bias voltage), temperature driftFeedbacks cannot currently compensate for small drifts

Outside the ASIC:Clock shared in “columns” across boards – currently unterminated tracesPath length differences in FPGA for different ASICs Crosstalk between channels

Comparator Response

ADCs are Wilkinson-style ramp comparators

Fires when ramp exceeds stored voltageSignals stored with DC offset to fit into ADC’s dynamic range

Offset varies cell-to-cell = pedestal correction

Comparator response is nonlinearTransfer function varies for each storage cell

Examples here from IRS2 and TARGET5 ASICs (same comparator as IRS3B)

AC vs. DC response

Transfer functions measured with DC inputs, but AC response may be differentOne example: persistence

Voltage has some dependence on previous-stored voltageWill show “ghost” pulse for 1+ cyclesWill also reduce pulse heightShould primarily affect large pulses

Example from PSEC3 chip at right

Input Coupling

Multiple components:Amplifier bandwidthCoupling into ASIC sample cells

Can depend on timing parameters of ASIC – how many sampling cells are currently connected

Definite apparent gain in pulser data, but spectral content differs between laser and pulser data

Corrections not the sameHard to measure gain without fixed-height samples

Need calibration signals that look like MCP-PMT signals!

Laser Pulser

Overconstrained Timing

Timing within each 128 samples controlled by delay lineTiming controlled by bias on delay lineEach 128 sample set started with input clock

Incorrect biasing may end sample too soon (gap between samples) or too late (overlap between samples)

Sample-to-Sample Timing Uncertainties

Delay lines stages can have varying delays between them

Has strong impact on timing resolution

Measurement method:Inject fixed-amplitude pulses at known timeUse simple measurement to determine timing (threshold + interpolation)Significant structure seen

Delay lines also dependent onnoise on bias voltage, temperature

Very difficult to recover (requiresdetailed knowledge of noise spectrum)Evidence is seen of bias voltage noiseEvidence seen of temperature driftas well

Feedback Loops

FPGA firmware contains several feedback loops to keep timing, voltages stable

Evidence seen that sampling rate varies slightly at both smaller and larger scalesFeedback loops in FPGA cannot compensate for small drifts

Outside the ASIC

Channel-by-channel variation in t0 of up to several ns seen

Clock lines shared by 4 ASICs (across 4 boards)

Traces currently unterminated, may be causing distribution of start times

Each time FPGA design goes through place-and-route, different delays get set for different signals

Laser tests show ~2.1% crosstalk effect in MCP-PMT

Currently removed by ADC cut, but investigation into separation by both ADC and time underway

Current Status of Calibrations

Voltage: pedestal correction onlyKurtis Nishimura working on proper gain correction

Timing:Large-scale t0 correctionsSample-by-sample timing corrections

Complete this list!

iTOP Analysis Framework (topcaf)

Pulser Data

There are two sample buffers with a depth of 64 samples

These need to be corrected for each ASIC (8 channels/ASIC)ASIC correction, so only one channel per ASIC was pulsed

Image Plots

Mapping of x-y positioning to global channel number

Pulser Raw Image

ASIC correction, so one channel per ASIC was pulsed1 problematic SCROD during these runs (4 ASICs were affected)

Pulser Sample to Sample Corrections

There are two sample buffers with a depth of 64 samplesThese need to be corrected for each ASIC (8 channels/ASIC)

‘Even’ buffer ‘Odd’ buffer

Pulser Sample to Sample Corrections

Before correction, two obvious peaks appearAfter correction, single peak seen

Pulser Resolution

One entry per ASIC in histogram (64 total)4 ASICs with > 100 ns timing

still investigating, but all row 0 col 2 ASICs – may be FPGA issue

Pulser Corrected Image

Corrected image much cleaner, aligned properly

Laser Data

At LEPS, laser injected into bar via fiber at far cornerResulted in very uneven coverage

Left/right differences, hot spot, and almost no photons in lower PMTsDifference in arrival times at PMTs across the bar

4cm = ~193cm in quartz

2.54 m

0.45 m

2.58 m

Laser Image with Pulser Corrections

Additional timing offsets from laser trigger delays and PMT/PMT wiring offsets

Laser Resolution

Laser resolution after pulser corrections worse than pulser resolution (~140 ps vs. ~70 ps)

Pulser Laser

Laser Resolution (time walk)

Additional calibration of time walk due to varying amplitude requiredCurrently just ad-hoc correctionlatest???

Laser Resolution (time walk)

Ad-hoc correction recovers pulser timing in laser data (~90 ps)

Final Laser Image

Clear image of laser wavefront reflectingMore data processing needed to measure resolutionsInvestigating methods of recovering lower PMTs (256+)

Beam Image (cos θ = 0, x=0)

Using ADC range cut Need proper gain calibration

Beam Image (cos θ = 0.39, x=-1.0 cm)

ADC range cut , need proper adc amplitude calibration work is ongoing

Beam Image (cos θ = 0.37, x=20.0 cm)

ADC range cut , need proper adc amplitude calibration work is ongoing

More on framework?

MC details?Versions? Backgrounds?