oki semiconductor sospjml8142pdse-01 · pdf file · 2005-01-20oki semiconductor...

OKI Semiconductor SOSPJML8142PDSE-01 Issue Date: Sep. 1, 2004

ML8142GD/ML8142HB Preliminary Low-power GPS down converter

GENERAL DESCRIPTION The ML8142 is a highly integrated GPS (Global Positioning System) down converter LSI, designed to receive the L1 signal at 1575.42MHz. The ML8142 integrates LNA (Low Noise Amplifier), VCO (Voltage Controlled oscillator), PLL (Phase Locked Loop), mixers, and IF sampling functions. The high level of integration reduces the external component count to just 5 passives in addition to power supply de-coupling and a 16.368 MHz crystal. Furthermore, elimination of the need for an external VCO resonator and LNA matching components reduces the critical off-chip RF circuitry to zero. Combined with the 5.0 x 5.0 mm QFN package (ML8142GD) or 2.66 x 2.66 mm LGA package (ML8142HB), this results in a very small circuit footprint. The ML8142’s small size and low BOM requirement is complemented by just 24 mW typical operating power consumption. Digitally controlled shutdown modes enable the 16.368 MHz clock signal to the baseband processor to be maintained separately from operation of the rest of the receiver. The LNA including input and output matching components reduce off chip components. An I and Q mixers down converts the RF signal to a 4.092 MHz IF. The image reject IF filter feeds a limiting amp and 1 bit ADC. The output signal is selectable for a 1 bit quantized 4.092 MHz digital IF signal latched by 16.368MHz clock or 4.092MHz analog IF signal. The ML8142GD & ML8142HB are manufactured in UTSi® CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. UTSi® is registered trademarks of Peregrine Semiconductor Corporation, USA. FEATURES

Low voltage operation: 1.5V (typ.) Low power consumption: 24mW/16mA (typ.). Single conversion radio with a low IF architecture. On-chip LNA including input and output matching. On-chip crystal oscillator can be powered up independently. Fully integrated IF filters, VCO, VCO tank circuit, and PLL reducing bill-of-material (BOM) . User selectable analog or digital data output modes. Suitable for 16.3680MHz systems. Package: ML8142GD 5.0mm x 5.0mm 32-pin plastic QFN ML8142HB 2.66mm x 2.66mm 25pin LGA (W-CSP)

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OKI Semiconductor ML8142GD/ML8142HB

BLOCK DIAGRAM

SYNTHN=96, R=1

Fcp=16.368MHz

LoopFilter

Polyphase NetworkQuadrature generation

LNA RF AMP

MIXERS IMAGE REJECTIF FILTER

LIMITING AMP

fosc=1571.328 MHz

D

CLK Q

1 BIT ADC

4.092MHz

SAMPLEDDATA OUT16.368 Mb/s

VCO

BPF

2

RF_IN

1575.42 MHz

CLK_OUT16.368 MHz

DATA_OUT

MIX_IN

RX_EN

LNA_OUT

V_TUNE

OSC_EN

2 2

CRYSTALOSCILLATOR

fosc

=16.368 MHz XTAL1

XTAL2

COARSETUNE

2

2

2

2

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PIN CONFIGURATION: ML8142GD 5.0mm x 5.0mm 32pin QFN (Top View)

1

2

3

4

5

6

9 10 11 12 13 14

24

23

22

21

20

19

30 29 28 27 26 25

LNA_OUT

NC

VDD2_LNA

VDD

_MIX

VDD

_LO

BUF

TEST

_X

CLK_OUT

DATA_OUT

SDIN

LEN

VDD_PLL

VDD

_XTA

L

XTA

L1

XTA

L2

VDD

_LIM

7

8

RX_EN

15 16

VDD

_VCO

DA

TA_M

OD

E

18

17

V_TUNE

32 31

VDD1_LNA

SCK

NC

VDD_RFAMP

NC

MIX

_IN

OSC

_EN

TEST

SLEW

VDD

_DIG

VDD

_IFF

ILT

IFTE

ST

LNA_

IN

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PIN DESCRIPTIONS: ML8142GD

Pin No.

Symbol Type Initial Value

Active Level

Description Note

3 LNA_OUT AO - - LNA output, 50Ω single ended 4 VDD1_LNA V - - Power supply for LNA 5 VDD2_LNA V - - Power supply for LNA 6 VDD_RFAMP V - - Power supply for RF AMP 7 RX_EN DI - H Enable control for receiver (all circuits except reference

oscillator and data registers), active high input

9 MIX_IN AI - - Mixer input signal, 50Ω single ended 10 OSC_EN DI - H Enable control for reference oscillator, active high input 11 VDD_MIX V - - Power supply for mixer 12 VDD_LOBUF V - - Power supply for LO buffer 13 TEST_X AO - - Test pin 14 TEST AO - - Test pin 15 VDD_VCO V - - Power supply for VCO 16 DATA_MODE DI - L Output mode setting (H=Digital Mode, L=Analog Mode) 17 SLEW DI - L Output driver slew rate setting

(H=Strong Mode, L=Weak Mode)

18 VTUNE AIO - - Charge pump output / VCO control voltage input 19 VDD_PLL V - - Power supply for PLL 20 LEN DI L H SPI enable 21 SDIN DI L - SPI data 22 SCK DI L - SPI clock 23 DATA_OUT DO - - Data output

24 CLK_OUT DO - - Buffered version of crystal osc. output / D-type clock 25 VDD_DIG V - - Power supply for Digital Output and A/D 26 VDD_LIM V - - Power supply for limiting amp 27 XTAL2 AIO - - Connection to crystal 28 XTAL1 AIO - - Connection to crystal 29 VDD_XTAL V - - Power supply for crystal oscillator 30 VDD_IFFILT V - - Power supply for IF filter

31 IFTEST AO - - Test pin 32 LNA_IN AI - - LNA Input Die Pad

GND G - - Ground connection for all circuits via die pad

AI: Analog input, AO: Analog output, AIO: Analog input /output DI: Digital input, DO: Digital output, DIO: Digital input /output V: Power supply, G: Ground

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PIN CONFIGURATION: ML8142HB 2.66mm x 2.6 mm 25pin LGA (Top View)

VDD_VCO VDD_ MIX OSC_EN

V_TUNE VDD_ PLL

DATA_ MODE VSS_2 MIX_IN RX_EN

VDD_ LNA

VSS_3 VSS_4 LNA_ OUT

DATA_OUT

VDD_ DIG XTAL_2

VDD_ XTAL

CLK_ OUT

VDD_ LIM XTAL_1

VDD_ IFFILT VSS_1 LNA_IN

A B C D E F

SLEW

6

5

4

3

2

1

Index Mark

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PIN DESCRIPTIONS: Ml8142HB

Pin No.

Symbol Type Initial Value

Active Level

Description Note

E4 LNA_OUT AO - - LNA output, 50Ω single ended D3 VDD_LNA V - - Power supply for LNA F2 RX_EN DI - H Enable control for receiver (all circuits except reference

oscillator and data registers), active high input

E2 MIX_IN AI - - Mixer input signal, 50Ω single ended E1 OSC_EN DI - H Enable control for reference oscillator, active high input D1 VDD_MIX V - - Power supply for mixer B1 VDD_VCO V - - Power supply for VCO C2 DATA_MODE DI - L Output mode setting (H=Digital Mode, L=Analog Mode) A1 SLEW DI - L Output driver slew rate setting

(H=Strong Mode, L=Weak Mode)

A2 VTUNE AIO - - Charge pump output / VCO control voltage input B2 VDD_PLL V - - Power supply for PLL A5 DATA_OUT DO - - Data output A6 CLK_OUT DO - - Buffered version of crystal osc output / D-type clock B5 VDD_DIG V - - Power supply for Digital Output and A/D B6 VDD_LIM V - - Power supply for limiting amp C5 XTAL2 AIO - - Connection to crystal C6 XTAL1 AIO - - Connection to crystal

D5 VDD_XTAL V - - Power supply for crystal oscillator D6 VDD_IFFILT V - - Power supply for IF filter F6 LNA_IN AI - - LNA Input E6 VSS_1 G - - Ground connection D2 VSS_2 G - - Ground connection C4 VSS_3 G - - Ground connection D4 VSS_4 G - - Ground connection

AI: Analog input, AO: Analog output, AIO: Analog input /output DI: Digital input, DO: Digital output, DIO: Digital input /output V: Power supply, G: Ground

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FUNCTIONAL DESCRIPTION LNA The internal LNA has sufficient performance to be connected directly to a local passive antenna in an integrated module. The LNA includes input decoupling and matching close to 50Ω for connection to a local passive antenna in an integrated module, and it also includes output decoupling and matching close to 50Ω for connection to the integrated mixer input directly or via an external filter. Attention should be paid to track lengths and interference throughout the design. Mixer RF Input The Mixer RF input pin, MIX_IN, is a single ended 50Ω input, designed to interface either to the LNA_OUT pin or to the output of an external filter. The image reject IF filter ensures that the receiver’s full sensitivity is achieved without need for an external filter. However, for applications where additional selectivity is required in excess of that provided by the integrated filters, an external filter can be added between the LNA_OUT and MIX_IN ports. An impedance close to 50Ω is presented at each pin. PLL and Loop Filter The entire phase-locked loop generating the local oscillator for the mixer is contained on-chip, with the exception of the loop filter. Recommended values provided on the application circuit provide optimum performance in most applications. The capacitors may be ceramic dielectric types, with either C0G/NP0 or X7R dielectric. Higher capacitance per unit volume dielectrics should be avoided to maintain optimum phase noise and minimize microphony. The PCB layout should keep the track from the VTUNE pin to the loop filter as short as possible to minimize noise pickup. Crystal Oscillator The crystal oscillator is a Pierce configuration. The application circuit is designed to work with parallel resonant crystals with a load capacitance of 12pF. The PCB layout should avoid excessive track length between XTAL1 and XTAL2 pins and the crystal. The capacitors at each terminal of the crystal should be mounted adjacent to the crystal and have a low impedance connection to the ground plane. Tracking and data recovery systems in GPS basebands use comparatively long time-constants to extract phase information from the GPS signals. Therefore it is vital that the receiver crystal is very well isolated from changes in temperature and mechanical stress. ML8142 provides good performance with inexpensive low-profile HC49 surface mount crystals and some ceramic-packaged devices. The Oscillator Enable (OSC_EN, pin 10) input can be raised independently of Receiver Enable (RX_EN) to allow the oscillator to provide clock to the base-band processor without incurring the current consumption of the rest of the receiver. The ML8142 can be used with an external reference oscillator. The external reference can be supplied as either a sinusoidal or CMOS signal. The table below indicates, for each case, the correct combination of input pin, coupling and setting for the oscillator enable pin.

Type Coupling Input pin OscEnCMOS DC 27 LOsine AC 28 HI

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ABSOLUTE MAXIMUM RATINGS

Parameters Symbol Min. Max. Unit Power Supply Voltage VDD -0.3 +2.75 V Voltage on Any Pin with respect to GND -0.3 VDD+0.3 V Storage Temperature TSTG -65 +150 °C

RECOMMENDED OPERATING CONDITIONS

Parameters Symbol Min. Typ. Max. Unit Power Supply Voltage VDD 1.425 1.5 1.575 V Operating Temperature Ta -40 +25 +85 °C Digital Input High Voltage VIH 0.8xVDD VDD V Digital Input Low Voltage VIL 0 0.2xVDD V Digital Input Rise Time tir 20 ns Digital Input Fall Time tif 20 ns Digital Output Load CDL 10 pF

ELECTRICAL CHARACTERISTICS DC Characteristics

Power Supply Current Parameters Symbol Min. Typ. Max. Unit

Total Supply Current, All Circuits Active IDDO 16 mA Supply Current, Oscillator Only Active IDDO_OSC 1 mA Supply Current, No Circuits Active IDDS 10 µA

Digital Input & Output

Parameters Symbol Min. Typ. Max. Unit Input Leakage Current, VI=VDD IIH 1 µA , VI=0V IIL -1 µA Output High Voltage, IOH=0.5mA VOH 0.8xVDD VDD V Output Low Voltage, IOL=-0.5mA VOL 0 0.2xVDD V Input Capacitance CIN 5 pF

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Detailed Characteristics (Condition: VDD=1. 5V, Ta=25°C)

LNA Parameter Symbol Condition Note Min. Typ. Max. Unit

Supply Current IDDO RX_EN=’1’ 2 mA Forward Gain S21 FRF=1570MHz to 1580MHz

Pin=-80dBm

19 dB

Noise Figure NF FRF=1570MHz to 1580MHz 2.6 dB Input Return Loss S11 50 Ω System, Single Ended Input -10 dB Output Return Loss S22 50 Ω System, Single Ended Output -10 dB Input IP3 IIP3 Tones at 1575±5MHz @-60dBm -13 dBm Input Power at which Gain Falls by 1dB.

P1dB

-23

dBm

Recovery Time from –3dBm Input Overload Signal

tR 1 4 µsec

Note: (1) Tentative value. It may be changed after the product evaluation.

Receiver Parameter Symbol Condition Note Min. Typ. Max. Unit

Supply Current IDDO RX_EN=’1’ 8.5 mA Noise Figure NF FRF=1570MHz to 1580MHz

Input to ‘MIX_IN’

9.5 dB

Input IP3 IIP3 Tones At 1575±5MHz @-40dBm (Mixer and IF Filter Only)

-24 dBm

Input Return Loss S11 50 Ω System -10 dB Recovery Time From –30dBm Input Overload Signal

tR Tones At 1575±5MHz @-60dBm 1

4

µsec

IF Center Frequency fIF 4.092 MHz-3dB Bandwidth BW 2 MHzGroup Delay Variation, fC±BW/2

∆Tg 0.1 µsec

Attenuation at fC ±BW AV2 13 dB Attenuation at fC ±2xBW AV4 31 dB

Note: (1) Tentative value. It may be changed after the product evaluation.

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VCO and PLL

Parameter Symbol Condition Note Min. Typ. Max. Unit Supply Current IDDO RX_EN=’1’ 4.5 mA VCO Center Frequency fVCO 1571.328 MHz LO SSB Phase Noise at 1kHz Offset

L1K -65 dBc/Hz

LO SSB Phase Noise at 10kHz Offset

L10K -75 dBc/Hz

LO SSB Phase Noise at 100kHz Offset

L100K -80 dBc/Hz

Crystal Oscillator

Parameter Symbol Condition Note Min. Typ. Max. Unit Supply Current, Crystal Oscillator and Clock Buffers

IDDO OSC_EN=’1’, RX_EN=’0’, CLK_OUT=on, but DATA_OUT=off

0.6 mA

Oscillator Frequency fXTAL 16.368 MHzCrystal Parameters Mode Frequency ESR CLOAD

Parallel Fund. 16.368

12

50

MHzΩ pF

Timing Characteristics

Parameter Symbol Note Min. Typ. Max. Unit Receiver Startup Time (RX_EN to valid data out) 1 msec Crystal Oscillator Startup Time (OSC_EN to reference output within 10 ppm)

2 msec

VCO Self Calibration (VDD applied to RX_EN to functional)

1 2.5 msec

Note: (1) The VCO goes through a self-calibration routine when power is first applied. RX_EN and OSC_EN

are overridden during this time. This calibration event does not need to be repeated if the receiver is put into standby mode with RX_EN and OSC_EN control signals.

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Clock and Data Outputs

Conditions: CL=10pF, VDD=1.5V, Ta=25°C Parameter Symbol Note Min. Typ. Max. Unit

Clock Period tPER 60 nsec Clock Low Width tPWL 20 nsec Clock High Width tPWH 20 nsec Clock to Data Delay Time tDEL 1 10 nsec Setup Time tSETUP 1 10 nsec Hold Time tHOLD 1 15 nsec Rise and Fall Time, 10-90% (CLK_OUT & DATA_OUT) Fast Slew Mode Slow Slew Mode

tR/F 1

5 15

nsec nsec

Note: (1) Specifications for tDEL, tSETUP, and tHOLD are applicable only in digital DATA_OUT mode. Specification for tR/F applies in both digital and analog DATA_OUT mode. DATA_OUT is a CMOS logic compatible output signal, with VOH > 0.8VDD and VOL < 0.2VDD (for IOH, IOL < 0.5mA).

Output Data Timing Diagram tPER =60ns min tPWH =20ns min

tPWL =20ns min

tR/F =15ns maxtDEL =10ns max

tR/F =15ns max

tHOLD =15ns min

tSETUP =10ns min

CLK_OUT

DATA_OUT

tPER =60ns min tPWH =20ns min

tPWL =20ns min

tR/F =15ns maxtDEL =10ns max

tR/F =15ns max

tHOLD =15ns min

tSETUP =10ns min

CLK_OUT

DATA_OUT

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Application Circuit

LNA_

IN

VDD_LNA1

IFTE

ST

LNA_OUT

VDD_LNA2

RX_EN

CLK_OUT

XTAL

_1

XTAL

_2

VDD

_DIG

VDD_PLL

TUNE

VDD

_FIL

T

SPI_DATA

SPI_CLK

SPI_EN

VDD

_LIM

DATA_OUT

MIX

_IN

VDD

_MIX

VDD

_LO

BUF

TEST

VDD

_VC

O

TES

T_X

DAT

A_M

OD

E

Vdd

Enable from Processor

Vdd

Vdd

Vdd

Clock Output

VDD_RFAMP

OSC

_EN

Enab

le fr

omPr

oces

sor

SLEW

Data Output

VDD

_XTA

L

NC

NC

NC

Con

trol f

rom

Proc

esso

r

Control fromProcessor

Control fromProcessor

20p

20p

20p 100n

20p

100n

82p

2.7n

3.3k

100n

100n

1２ｐ 1２ｐ

Note: The load capacitance of the Crystal Oscillator is 12pF. But this value is subject to change according to the PCB trace. Please adjust this capacitance on your specific board.

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PACKAGE INFORMATION ML8142GD: 5.0mm x 5.0mm 32pin QFN package

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ML8142HB: 2.66mm x 2.66mm 24pin LGA (WCSP) package

0.5mm

2.66mm

2.66mm

0.40mm NON ACCUMULATIVE

NOTES FOR MOUNTING THE SURFACE MOUNT TYPE PACKAGE The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). MISCELLANEOUS Electrostatic Discharge (ESD) Precautions When handling this UTSi® device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rationg specified. Latch-Up Avoidance Unlike conventional CMOS devices, UTSi® CMOS devices are immune to latch-up.

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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements.

Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation

for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.

3. When designing your product, please use our product below the specified maximum ratings and within the

specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation

resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range.

5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted

by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof.

6. The products listed in this document are intended for use in general electronics equipment for commercial

applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems.

7. Certain products in this document may need government approval before they can be exported to particular

countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these.

8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.

Copyright 2004 Oki Electric Industry Co., Ltd.

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oki semiconductor sospjml8142pdse-01 · pdf file · 2005-01-20oki semiconductor...

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