power consumption at circuit or logic level in circuit

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its a brief description about power consumption in circuit and reduction techniques.

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  • 1 An assignment on LOW POWER VLSI DESIGN (EEC7208) POWER CONSUMPTION IN CIRCUIT By Anil Kumar Yadav Reg. no.: 13304025 (M.Tech electronics) Department Of Electronics Engineering School Of Engineering and Technology Pondicherry University
  • 2 Table of content Content Page no. 1. Introduction 1.1 Is Power Really A Problem? 1.2 Do We Need To Bother With Power? 1.3 Why Power Matters in SOC? 4 4 4 4 2. Sources of power consumption in digital CMOS circuits 2.1 Short-circuit power 2.2 Leakage power 2.3 Static Power 2.4 Switching power 5 5 5 6 6 3. Low-Power Design Techniques 7 4. Power reduction techniques at circuit level: 4.1 Transistor and Gate Sizing of an Inverter 4.2 Chain Equivalent Pin Ordering 4.3 Network Restructuring and Reorganization 4.4 Transistor Network Partitioning and Reorganization 4.5 Flip Flops & Latches design 4.6 Self-gating Flip-flop 4.7 Combinational flip flop 4.8 Double Edge Triggered flip flop 4.9 Low Power Digital Cell Library 7 8 10 11 12 12 14 15 15 16 5.CONCLUSION 17 6.REFERENCES 18
  • 3 Abstract. In designing digital circuits and systems, minimizing power consumption has gained considerably insignicance compared to the traditional cost metrics of silicon area, performance and testability. The increasing importance of low power consumption is due to the ever decreasing feature sizes of microelectronic circuits, higher clock frequencies and larger die sizes, as well as the growing number of mobile, battery-operated systems. To contain power optimization, modern design methodologies therefore allow optimizing power on all levels during the design flow, from system level down to technology level. These optimizations are either applied manually by the design engineer or automatically using CAD tools. This report gives an overview of the state-of-the-art in minimizing power consumption at circuit levels of the design of digital circuits and systems.
  • 4 1. Introduction During the desktop PC design era VLSI design efforts have focused primarily on optimizing speed to realize computationally intensive real-time functions such as video compression, gaming, graphics etc. As a result, we have semiconductor ICs that successfully integrated various complex signal processing modules and graphical processing units to meet our computation and entertainment demands , which need to pack all this without consuming much power. The strict limitation on power dissipation in portable electronics applications such as smart phones and tablet computers must be met by the VLSI chip designer while still meeting the computational requirements. Reducing the total power consumption in such systems is important since it is desirable to maximize the run time with minimum requirements on size, battery life and weight allocated to batteries. So the most important factor to cosider while designing SoC for portable devices is 'low power design'. 1.1 Is Power Really A Problem? Scaling of technology node increases power-density more than expected. CMOS technology beyond 65nm node represents a real challenge for any sort of voltage and frequency scaling Starting from 120nm node, each new process has inherently higher dynamic and leakage current density with minimal improvement in speed. Between 90nm to 65nm the dynamic power dissipation is almost same whereas there is ~5% higher leakage/mm2.Low cost always continues to drive higher levels of integration, whereas low cost technological breakthroughs to keep power under control are getting very scarce. Modern System-on-Chip demand for more power. In both logic and memory, Static power is growing really fast and Dynamic power kind of grows. Overall power is dramatically increasing. If the semiconductor integration continue to follow Moore's Law, the power density inside the chips will reach far higher than the rocket nozzle. 1.2 Do We Need To Bother With Power? Power dissipation is the main constrain when it comes to Portability. The mobile device consumer demands more features and extended battery life at a lower cost. About 70% of users demand longer talk and stand-by time as primary mobile phone feature. Top 3G requirement for operators is power efficiency. Customers want smaller & sleeker mobile devices. This requires high levels of Silicon integration in advanced processes, but advanced processes have inherently higher leakage current. So there is a need to bother more on reducing leakage curret to reduce power consumption. 1.3 Why Power Matters in SOC? Power Management matter in System on Chip due to following concerns a)Packaging and Cooling costs. b)Digital noise immunity, c)Battery life (in portable systems) d)Environmental concerns.
  • 5 2. Sources of power consumption in digital CMOS circuits: There are four components which contribute to the average power consumption Pavg of a digital CMOS circuit: Pavg = Pleakage + Psc + Pswitching + Pstatic; Where Switching power P = CV2 f Short circuit power P = IscV Leakage power P = IleakageV Static power P = IstaticV : switching activity factor 2.1 Leakage power Leakage power is caused by substrate injection at p/n junctions and subthreshold effects which are primarily determined by fabrication technology. It contributes less than 1% to the average power consumption and can therefore be ignored for our purposes. It is, however, important in the context of ultra low-power systems with a very small VDD, as used in microelectronic systems for medical applications. The PMOS and NMOS transistors used in a CMOS logic circuit commonly have non-zero reverse leakage and sub-threshold currents. These currents can contribute to the total power dissipation even when the transistors are not performing any switching action. The leakage power dissipation, P leakage is caused by two types of leakage currents. The leakage power dissipation, P leakage is caused by two types of leakage currents a) Reverse-bias diode leakage current b) Sub threshold current through a turned-off transistor channel 2.2 Short-circuit power Short-circuit power is caused by currents which temporarily occur when both the n- and p-parts of a gate are open while the gate is switching. Suppose the input X to the CMOS inverter in Figure 2 is making a transition from logic '0' to logic '1'. While the p-device is being turned OFF and the n-device is being turned ON, there is a short period of time during which there is a direct current path from VDD to ground. This current is called the short-circuit current Isc. It typically accounts for 10% to 20% of the overall power consumption.
  • 6 The short-circuit dissipation of the gate varies with the output load and the input signal slope. The short-circuit dissipation decreases linearly (roughly) in both absolute terms and a fraction of the total dissipation as the output load is increased to a critical value and then it will increase again rapidly . For simplicity a symmetrical inverter (i.e., N = p and VTn = -Vtp;) and a symmetrical input signal (rise time = fall time) are considered. I = /2(Vin V T)2 for 0 I Imax Imean = 1/T 0 T I(t) dt = 2* 2/T t1 t2 /2 (Vin (t) VT)2 dt Assuming the rising and falling portions of the input voltage waveform to be linear ramps, Vin(t) = t* VDD/ Imean = 2*2/T(Vt/Vdd) /2 /2(t*VT/ VT)2 dt Let = (VT/)t - VT Imean = - 2/T(Vt/Vdd) /2 d Imean = 1/12*/VDD(VDD VT)3 /T The short-circuit power dissipation of an unloaded inverter is PSC = /12(VDD VT)3 /T If the inverter is lightly loaded, causing output rise and fall times that are relatively shorter than the input rise and fall times, the short-circuit dissipation increases to become comparable to dynamic dissipation To minimize dissipation, an inverter should be designed in such a way so that the input rise and fall times are about equal to the output rise and fall times. 2.3 Static Power Static power is the power dissipated by a gate when it is not switching that is, when it is inactive or static. Ideally, CMOS (Complementary Metal Oxide Semiconductor) circuits dissipate no static (DC) power since in the steady state there is no direct path from Vdd to ground. This scenario can never be realized in practice, since in reality the MOS transistor is not a perfect switch. There will always be leakage currents, sub threshold currents, and substrate injection currents, which give rise to the static component of power dissipation. The largest percentage of static power results from source-to-drain sub threshold voltage, which is caused by reduced threshold voltages that prevent the gate from completely turning off. 2.4 Switching power The switching power, also called dynamic or capacitive power, is by far the most signi_cant component and accounts for approximately 80% of the overall power consumption. Switching power is dissipated when the capacitive load C(y) of a CMOS gate is being charged by the current Iswitch through the p-device to make a transition from ground to VDD. The energy required for this transition is C(y)V2 DD. Power-consuming transitions occur at a frequency
  • 7 1/2(y)fclk proportional to the clock frequency fclk, where (y) is the probability of signal y to make a '0' to '1' or '1' to'0' transition. The total switching power of a circuit is therefore: above Eq. shows that the switching power increases linearly with the clock frequency. To reduce the switching power even for increasing clock frequency, we therefore have the following opportunities: Since the supply voltage VDD influences the Pswitching quadratically, it is most effective to reduce VDD. However, a lower supply voltage also results in slowe