1 draft – work in progress - not for publication 12-13 april 2005 – itrs public conference...
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1DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
Design and System Driver Chapters
Spring Meeting April 2005Munich, Germany
Design TWG (Europe, Asia, and U.S.)
Albin, Arledge, Asada, Bernstein, Bertacco, Blaauw, Blanton, Brederlow, Briere, Carballo, Chen, Cohn, Cottrell, Darringer, Edwards, Furui, Gowda, Guardiani, Hiwatashi, Kahng, kashiwagi, Kawahira, Kozawa, Ishibashi, Kravets, Martin, McMillan, Nassif, Pan, Macd, Nukiyama, Pitchumani, Pixley, Rosenstiel, Read, Rodgers, Sakallah, Smith, Soma, Stok, Vertregt, Wilson, Yamamoto, Yamada, Yeh
2DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
2005 Spring Deliverables
1. 10 new table drafts quantify design technology trends– Final version targeted by June
2. DFM preliminary model enables variability roadmap– DFM roadmapping tool + interface with other groups
3. Draft SoC cost model provides new type of driver– SoC model quantifies productivity and architecture
trends
3DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
TimelineDate Milestone
April 12 ITRS Europe meeting starts
Current tables/roadmaps presented for review
June 10 DFM preliminary roadmap complete
Revised tables/roadmaps completed
NEMI roadmap mapping first version complete
Draft Design and System Drivers due to editors
July 11 ITRS USA meeting starts
Revised tables/roadmaps presented for review
DFM roadmap presented for review
NEMI mapping proposal for review
Final Design Chapter due to editors
Sep 19 Finalized tables/roadmaps
NEMI mapping, DFM roadmap finalized
ITRS 2005 content frozen
4DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
Design: Content organization
Promotion of key design challenges – Small subset of them to top-level ORTC
Design process
System design
Logic/circuitPhysical D
Design verification
Design Test
DFM(new)
Productivity Power DFM Interference Reliability
General
Selection
Mapping
5DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
Design: Content organization (II)
Scope
Complexity and Crosscutting Challenges
Design Technology Challenges
- Overall Challenges (5 challenges + table)
- Design Methodology Trends (text)
- System-level Design
- Logical, Circuit, and Physical Design
- AMS and RF-specific DT Trends and Challenges (revised)
- Design Verification
- Design Test
6DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
Detailed Table Status
Section Requirements Solutions
System Yes, draft Yes, draft
Logic/ckt/physical Yes, draft Yes, row definitions
Verification Yes, draft Yes, row definitions
Design Test Yes, draft Yes, draft
DFM Yes, draft Yes, draft
Targeting 50-60 new rows– Leads: Rosenstiel, Soma, Bertacco, Kravets, Nassif/Kahng
Next steps– Incorporate input until final version – Complete coloring
7DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
New Table: System-Level Requirements
Year of Production 2004 2007 2010 2013 2016 Driver
Technology Node hp90 hp65 hp45 hp32 hp22
% design block reuse 30 37 43 48 54 SOC
# available platforms 24 20 15 12 10 SOC
% available platforms supported by tools
1 10 50 70 90 SOC
% deviation of high level estimates (performance, area, power, costs)
50 40 30 20 10 SOC
% SOC reconfigurability (SW and/or HW)
20 28 35 42 50 SOC
% analog synthesizability (vs. digital)
10 17 24 32 40 SOC
Source: Wolfgang Rosenstiel’s Team
8DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
New Table: System-Level Solutions
Source: Wolfgang Rosenstiel’s Team
Technology Node
200720082006
20052009 2012 2015 2018
20102011 20132014 20162017 20192020
Research Required
System-level component reuse
Automated Interface Synthesis
Explicit system-level energy-performance trade-off
Multi-fabric implementation planning (AMS, RF, MEMS, …)
SW-SW and SW-HW co-design and verification
On-chip network design methods
Chip-package co-design methods
Development Pre-Production Improvement
Time during which research, development, and qualification/pre-production should be taking place for solution.
hp70 hp50 hp18hp25hp35 hp152021
9DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
Requirement Metric
asynchronous global signaling #handshake-related components
parameter uncertainty %-effect (on sign-off delay)
simult. analysis objectives # of objectives during optimization
MTTF contribution reliability factor
circuit families # of circuit families in a design
analog content synthesized % of a design
design on predictable platforms such as FPGAs (%)
adaptive/self-repairing circuits number of fuses per chip area unit
leakage per device, probability distribution
New Table: Logic/Ckt/Physical Requirements
Source: Victor Kravets’s Team
10DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
New Table: Logic/Ckt/Physical Requirements
2005 2007 2009 2012 2014 2016 2018 2020
comments hp90 hp65 hp45 hp32 hp16
% of a design driven by handshake clocking
5% 7% 15% 20% 20% 30% 30% 40%
%-effect (on sign-off delay)
5% 6% 10% 12% 15% 20% 20% 25%
# of objectives during optimization
4 4 6 8 8 8 8
reliability factor 1 1.2 1.4 1.8 2 2.2 2.5 2.7
# of circuit families in a single design(optimistic)
2 3 4
4
4
4
4
4
% of a designanalog synthesized
10% 15% 17% 30% 50%
# times per device 412
30 600 600
Source: Victor Kravets’s Team
11DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
New Table: Verification Requirements Verification requirements
Bugs •escape rate: bugs found after first tape out. •bugs found after system integration until tape-out Code coverage •percent of code coverage Functional coverage •percent of the projects where it is used •functional coverage goals for each thousand lines of HDL code •correlation of size of functional coverage goal vs. escape rate Tape-out criteria •examples: booting linux, total number of simulation cycle run, coverage.... Reuse •ratio of fresh verification infrastructure vs. reused •percent of reused infrastructure that is acquired from third parties Methodology •effort spent in formal verification vs. simulation/emulation (in engineering days) •effort spent in formal verification vs. simulation/emulation (in lines of HDL)
Source: Valeria Bertacco’s Team
12DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
New Table: DFT Requirements% components covered by DFT
1. DFT-support for test methodology of RX and TX circuit components for manufacturing defects and severe process variations. Note normal process variation and device mismatch should be comprehended in the analog design with compensation circuitry, which requires testing to assure its proper operation.
% parallel / % separate 2. DFT-support for parallel or separate test of TX/RX for fault diagnosis.
% control via TAP 3. Control of DFT features via JTAG or other industry-standard test access port.
Standard availability 4. DFT / ATE interface standard. Need to develop to encourage open test architectures and solutions. DFT methodologies must work in conjunction with ATE to support a comprehensive test methodology.
% re-use 5. Re-use of existing I/O circuit features to take measurements during test. Example: RX data clock recovery circuits can be re-used for a timing measurement.
% accessible / % reconfigurable 6. Accessibility and reconfigurability of component-level DFT features for system-level validation / characterization (i.e. system link health) and system test.
% hierarchical DFT 7. DFT-support for hierarchical system test and validation without descending to the component level.
% reduction in functional test 8. DFT-support for on-die pattern generation and checking to reduce / avoid cost for functional test pattern development.
% non-invasive test 9. DFT-support for non-invasive (non-intrusive) or minimally invasive (minimally intrusive) wafer level test.
% low-speed / % high-speed DFT 10. DFT for both low-speed and at-speed test of digital / analog / mixed-signal / RF systems.
%all-digital DFT 11. All-digital DFT for analog / mixed-signal / RF circuits and systems. DFT support for RF measurements (continuous method and / or modulated method).
Availability 12. Variable-sensitivity DFT.
Availability 13. DFT for DFY.
% correlation 14. DFT output correlation to existing specification-based test methods.
Quantization model and calculations 15. Quantization of DFT impact on system performance (noise, power, sensisitivity, bandwidth, etc.).
% DFT support 16. DFT-support to test multiple-input multiple-output RF systems.
Availability of FM (fault model) 17. Development of fault models / defect models appropriate for DFT-oriented test methods of digital / analog / mixed-signal / RF integrated systems.
% DFT CAD tool available 18. CAD tools to support DFT incorporation into digital / analog / mixed-signal / RF systems
Source: Mani Soma’sTeam
13DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
DFT Technology Requirements
Near-term Long-term
2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Technology node
hp90 hp65 hp45 hp32 hp22 hp16
% components covered by DFT
20 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
% parallel / % separate
20.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
55.0
60.0
65.0
70.0
75.0
80.0
85.0
90.0
% control via TAP
25.0 30.0
35.0
40.0
45.0
50.0
60.0
60.0
70.0
70.0
75.0
80.0
80.0
90.0
100.0
100.0
% re-use 30 30 35 35 40 40 40 45 45 50 50 60 60 70 70 70
% accessible / % reconfigurable
20.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
55.0
60.0
65.0
70.0
75.0
80.0
85.0
90.0
% hierarchical DFT
20 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
% reduction in functional test
20 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
% non-invasive test
30 35 40 45 50 55 60 65 70 75 80 85 90 90 100 100
% low-speed / % high-speed DFT
20 30.0
35.0
35.0
40.0
40.0
45.0
50.0
55.0
60.0
65.0
70.0
75.0
80.0
85.0
90.0
%all-digital DFT 30 35 40 45 50 55 60 60 60 60 80 85 90 90 100 100
% correlation 20 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
% DFT support 10 10 20 20 30 30 35 35 40 45 50 55 60 70 80 90
Availability of FM (fault model)
Analog FM
Analog FM
Analog FM
MS FM
MS FM
MS FM
RF FM
RF FM
RF FM
System FM
System FM
System FM
Improve
Improve
Improve
Improve
% DFT CAD tool available
30 35 40 45 50 55 60 65 70 75 80 85 90 90 100 100
14DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
New Table: DFM Requirements Near-term Long-term
year (2000-) 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20
DFM hp90 hp65 hp45 hp32 hp22 hp16
Mask cost ($m)
1.5
2.2
3
4.5
6
9
12
18
24
36
48
72
96
144
192
288
% Supply variability
10
10
?
10
?
10
?
10
?
10
?
10
?
10
?
10
?
10 10 10 10 10 10 10
?
% CD variability10
10?
10?
10 10 10 10 10 10 10 10 10 10 10 10 10?
% circuit performance variability
33 33 34 35 36 37 38 39 39 39 39 39 39 39 40 40
% circuit power variability
3 55 55 56 56 57 57 58 58 59 59 60 60 61 61 62
Source: Carballo/Nassif/Pan/Kahng/Guardiani/Brederlow/Wong
15DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
New Table: DFM Solutions
Detailed tables: DFM2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
Technology node hp90
hp65
hp45
hp32
hp22
hp16
Tools that account for mask cost in their algorithms
RET tools that are aware of circuit metrics (timing, power)
Radically-restricted rules
Statistical analysis and opt. tools and flows (Vdd, T, Vth)
Statistical leakage analysis and optimization tools
Architectures resistant to variability (redundancy, ECC)
Adaptable and redundant circuits
Post-tapeout RET interacting with synthesis, timing, P&R
Source: Carballo/Nassif/Pan/Kahng/Guardiani/Brederlow/Wong
16DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
2. SoC Cost Model Update, Inc. SW
Mobile /Consumer SoC
Memory
PE-1
Peripherals
PE-2 PE-n…
MainPrc.
Design process
System design
Logic/circuitPhysical D
Design verification
Design Test
DFM(new)
Productivity Power Manufac. Interference Reliability
General
Selection
Updated productivity table cost
Will preserve consistency
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($M
)
$1
$10
$100
$1,000
$10,000
1990
1992
1994
1996
1998
2000
2002
2004
2006
2008
2010
17DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
# of Processing Engines
1839
84
171
359
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
2004 2007 2010 2013 2016
Are
a R
ati
o
0
50
100
150
200
250
300
350
400
Nu
mb
er
of
PE
s
Overhead Area Main Memory Main Processor
Processing Engines Periferal # of PE
18DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
Processing Power Trends
1.0
3.3
11.3
34.8
135.0
1
10
100
1,000
2004 2007 2010 2013 2016
No
mari
zed
to
2004
Processing Power # of PE Device Performance
19DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
HW Design Productivity Requirements
1.01.6
2.8
4.8
8.5
0
1
2
3
4
5
6
7
8
9
2004 2007 2010 2013 2016
Pro
du
cti
vit
y (
No
mari
zed
to
2004)
0
10
20
30
40
50
60
70
80
90
100
Lo
gic
Desig
n S
ize [
M G
ate
]
New design size Reused design size Productivity for new designs
20DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
3. New DFM Section –Outline
INTRO DFM CHALLENGES -- NEAR TERM (>45 NM)
– MASK COST– DATA EXPLOSION– LIMITATIONS OF LITHOGRAPHY HARDWARE RESOLUTION– VOLTAGE SUPPLY AND THRESHOLD VARIABILITY– BEOL PLANARIZATION AND DIMENSIONAL VARIABILITY– HETEROGENEOUS COMPONENTS (AMS, MEMS, ERAM)– LEAKAGE AS A LIMITER OF MANUFACTURABILITY– VARIABILITY
DFM CHALLENGES -- LONG TERM (<45 NM)- UNCONTROLLABLE CD AND DOPING VARIABILITY- EXTREME DEVICE AND CIRCUIT VARIABILITY- RET-awareness IN DESIGN- PACKAGE, SYSTEM, AND SW VARIABILITY- BEOL PLANARIZATION AND DIMENSIONAL VARIABILITY
– DESCRIPTION OF VARIABILITY MODEL
21DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
DFM Variability Framework
NALeff Weff WL ttOX tILD
Vt
Intermediate parameters Intermediate parameters
“Gate” delay (power) “Wire” delay (power)
Performance (delay) Power (energy)
Rsheet
(Vdd, T)
Other TWGs (PIDS, Interconnect, etc.)
Actual (bottom-up) / required (top-down) variability
22DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference
Roadmapping DFM Issues inc. Variability
0%
20%
40%
60%
80%
2005 2007 2009 2011 2013 2015 2017 2019
50%52%54%56%58%60%62%64%
performance variability
power variability
Current recommendation– Not to extend 10% CD control beyond 15%
– Below 15% still unclear