1

Lucas-Lehmer Primality TesterPresentation 9March 29, 2006

Team: W-4

Nathan Stohs W4-1

Brian Johnson W4-2

Joe Hurley W4-3

Marques Johnson W4-4

Design Manager:

Prateek Goenka

Overall Objective: Modular Arithmetic unit with a creative use

2

Status• Finished

– Project Chosen– C simulations– Behavioral Verilog– Structural Verilog– Floor Plan– Schematics– Pathmill Simulation of Top Level

• In Progress– Layout– Layout Simulations

• To Do– More Layout/Simulations

3

Simulation Notes

• Top Level Schematic Simulation

• Full run of smallest “interesting” case (p=7)– 5 hours on new machines– 4 Gb disk space*

*now that new machines have /scratch, we can use them.

Tests are re-run nightly to preserve sanity.

4

New “low-power” Registers

• Registers were overdue for an overhaul.• Hacked together, very poor performance

characteristics.

• Researched, decided to attempt a low power, or at least cleaner, design.

• Register layout not begun, best time to change things.

5

Low Power Schematic

6

7

Measured Simulation Characteristics

• Clk-Q 175ps

• Rise 115ps

• Fall 100ps

• Power: 28.55uM @ 250 MHz

• Less than 1% savings.

• Top level sim results:– Old: 636.2 uM– New: 631.9 uM

8

On the other hand…

• Initial extractedRC came out pretty badly

• Rise, Fall, Clk-Q all 3x longer.

• Obviously must handle with care

• Unless they clean up very very well, stick to a safter, practically-just-as-good conventional design.

9

10

11

More Power To You

• Other things helped far more– Switched largest multiplexers to n-pass*– Re-wrote several counters, turn off when not

in use.– Removed unnecessary checking logic (only

relates to cases larger than we can test).

Power After Logic Changes: 438.7uM

30% less power. Embarrassingly better. Need to re-verify in detail.

12

16-bit Subtraction

13

Rise time, RC

14

15

16

17

18

19

General Purpose Shifter

20

Modular Adder

21

22

23

AreasModule Area (μm2)

Count 13,200*

Partial Product 38,000*

Sub 16 3,240

Compare 200*

ModP 5,600*

Registers 3,000*

Mod_add 5,200

FSM 3,000*

*Estimate

24

Top Level Schematic

25

Floorplan

26

Partial Product Progress

Blocks Instances Status

Sub16 3 DRC/LVS/sim

Shift Left 2 90% Layout

Shift Right 2 100% Layout

Muxes 2 DRC/LVS

Logic (~200 transistors)

1 0% Layout

FullAdder16 1 DRC/LVS

27

Overall Status

Blocks Instances Status

Mod Add 1 DRC/LVS/sim

ModP (shifter) 1 90% Layout

Sub 16 1 DRC/LVS/sim

FSM/Count 1 10% Layout

Registers 2 20% Layout

Compare 1 0% Layout

28

What’s Next

• Layout Forever

• Continue Simulating Layout

• extractedRC power

• Optimize

29

Problems

• Waveforms are correct, but not always pretty.

30

Questions?