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Lucas-Lehmer Primality TesterPresentation 11April 24th 2006

Team: W-4

Nathan Stohs W4-1

Brian Johnson W4-2

Joe Hurley W4-3

Marques Johnson W4-4

Design Manager: Prateek Goenka

Overall Objective: Modular Arithmetic unit with a creative use

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Status• Finished

– Project Chosen– C simulations– Behavioral Verilog– Structural Verilog– Floor Plan– Schematics– Pathmill Simulation of Top Level– Module Layout– Global Layout

• In Progress– Global Simulations

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Final Floorplan

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Floorplan

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Poly Layer Mask

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Metal1 Layer Mask

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Metal2 Layer Mask

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Metal3 Layer Mask

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Metal4 Layer Mask

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compare Propagation Delay

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partial_product Propagation Delay

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Propagation Delays

Module Schematic extractedRC

FSM 80ps 270ps

mod_p 769ps 944ps

mod_add 817ps 907ps

partial_product

-shift_left

-shift_right

-sub_16

1.11ns

780ps

779ps

144ps

-

964ps

976ps

167ps

count 645ps 954ps

compare 727ps 2.25ns

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Power Estimates

Module Schematic extractedRC

FSM 8.88uW 11.72uW

mod_p 60.63uW 77.80uW

mod_add 86.16uW 89.75uW

partial_product 368uW -

count 53.81uW 60.35uW

compare 131.1nW 1.98uW

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Design Specifications

Module Transistor

Count

Area

(µm²)

Transistor

Density

FSM 152 1,200 .13

mod_p 1,280 8,603 .15

mod_add 1,168 5,603 .21

partial_product 7,328 54,680 .13

count 1,412 8,320 .17

sub_16 576 2,934 .20

Registers 896 6,028 .15

compare 40 125 .32

Total 12,852 86,704 .15

Aspect

Ratio

2.45

0.79

2.40

1.16

6.79

4.49

4.76

2.90

1.01

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What’s Next

• Simulations on Global Design

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Questions?