arm a9 mpcore
Post on 28-Feb-2018
241 Views
Preview:
TRANSCRIPT
-
7/25/2019 Arm A9 Mpcore
1/25
ARM Cortex-A9
MPCore
Processor
Presented by-M. Jawwad RafqFA15-R01-017Ce no! "9#-$$$%$$55&'
-
7/25/2019 Arm A9 Mpcore
2/25
Cortex-A (er)es
Efcient application processors orevery level o perormance.
Application processors or OS anduser applications.
Processors in smartphones, tablets,notebooks, eBook readers etc.
-
7/25/2019 Arm A9 Mpcore
3/25
Cortex-A (er)es
Hih perormance, in a amily o lo!
po!er.
"orte#$A% sinle core processor or a
scalable multicore processor& t*e
Cortex-A9 MPCore +rocessor.
-
7/25/2019 Arm A9 Mpcore
4/25
'here is it used(
E#amples&$ Apple A) *iPhone +S, iPad , iPad mini-
-
7/25/2019 Arm A9 Mpcore
5/25
'here is it used( *-
E#amples&$ /010A 2era *3otorola 4oom, 1roid 4-
-
7/25/2019 Arm A9 Mpcore
6/25
'here is it used( *5-
E#amples&$ PlayStation /ita
-
7/25/2019 Arm A9 Mpcore
7/25
'hat are its specs(
"orte#$A% processors One to our
67 cache si8e per A% processor 79,5,9
6 cache 7; :B3H8>core *1hrystone
=enerally clocked bet!een ;??3H8 and=H8
Out$o$Order Superscalar Pipeline stae77
EO @ P
-
7/25/2019 Arm A9 Mpcore
8/25
'hat are its specs(
Branch Predicator
2echnoloy node +? nm to 9)nm
Supply /oltae 7.?)/
2ransistor "ount 9,??,???
Po!er "onsumption ?.) ' to 7.% '
Ca8elle Support 5D A3 traditional reisters, ;? eon
reisters
2humb$ instruction set
-
7/25/2019 Arm A9 Mpcore
9/25
eisters
A3 has 5D reisters in total, all o!hich are 5$bits lon.
7 dedicated proram counter
7 dedicated current proram statusreister
) dedicated saved proram status
reisters 5? eneral purpose reisters
79 reisters only visible in A3.
A particular SPS *saved proram
-
7/25/2019 Arm A9 Mpcore
10/25
eisters
-
7/25/2019 Arm A9 Mpcore
11/25
-
7/25/2019 Arm A9 Mpcore
12/25
Pipeline Staes in A%
-
7/25/2019 Arm A9 Mpcore
13/25
Presentation Overvie!
3icro$architecture
3emory System
-
7/25/2019 Arm A9 Mpcore
14/25
3icroarchitecture Overvie!
/ariable lenth, out o order, superscalarpipeline
2!o instructions are etched in one cycle
0ssue up to + instructions per cycle into&
Primary data processin pipeline
Secondary data processin pipeline
6oad$store pipeline
"ompute enine *P>EO- pipeline
-
7/25/2019 Arm A9 Mpcore
15/25
"orte#A% 3icroarchitecture
0nstructio
n etch
1ecode
0ssueenam
e
E#ecut
e
'rite
back
3emor
y
-
7/25/2019 Arm A9 Mpcore
16/25
0nstruction etch
0nstruction cache si8e& 79:B, 5:B, or 9+:B
Superscalar pipeline& etchin t!o instructions at once
Branch Prediction&
=lobal History BuFer& 7: G 79: entries
Branch$2aret Address "ache& )7 G +: entries
eturn stack o + # 5 bits
ast$loop mode& instruction loop that are smaller than 9+bytes oten complete !ithout additional instruction cache
accesses
-
7/25/2019 Arm A9 Mpcore
17/25
0nstruction 1ecode
Super Scalar 1ecoder$ "apable o decodin t!o ull instructions per
cycle
-
7/25/2019 Arm A9 Mpcore
18/25
ename
eister enamin$ esolvin data dependencies andunroll small loops by hard!are
$ /irtual renamin o reisters
-
7/25/2019 Arm A9 Mpcore
19/25
0ssue
0ssue can dispatch up to + instructions percycle
Out o order selection o instructions rom
-
7/25/2019 Arm A9 Mpcore
20/25
E#ecute
/ariable lenth E#ecutin Stae *7 G 5 cycles-
$ 3ost 0nstructions Inish !ithin 7 cycle$ 0nstruction !hich olds shits and rotates can take 5
cycles$ A11 r?, r7, r 6S6 r5 *5 cycle- 6oical shit let
immediate *6S6-
-
7/25/2019 Arm A9 Mpcore
21/25
3emory Hierarchy
"P
0nstruction
"ache
1ata
"ache
"P
0nstruction
"ache
1ata
"ache
"P
0nstruction
"ache
1ata
"ache
"P
0nstruction
"ache
1ata
"ache
Snoop "ontrol nit *S"-Accelerator"oherence
Port
6 "ache
3ain 3emory
"orte# A% 3Pcore
-
7/25/2019 Arm A9 Mpcore
22/25
67 caches
79, 5 or 9+:B Support or Security E#tensions
0 cache& 1 cache&
"P
1J 0J
"P
1J 0J
"P
1J 0J
"P
1
J
0J
S" A"P
6 "ache
3ain 3emory
"orte# A%3Pcore
A, R%'-b)tb/s
A, R%'-b)tb/s
-
7/25/2019 Arm A9 Mpcore
23/25
6 cache
Shared 7;:B to ;3B
"P
1J 0J
"P
1J 0J
"P
1J 0J
"P
1
J
0J
S" A"P
6 "ache
3ain 3emory
"orte# A%3Pcore
A, R%'-b)tb/s
A, R%'-b)tb/s
-
7/25/2019 Arm A9 Mpcore
24/25
Snoop "ontrol nit
0nteral part o cachememory systems
"onnects processors tomemory system throuhA40*Advanced E#tensible0nterace- interaces
"P
1J 0J
"P
1J 0J
"P
1J 0J
"P
1
J
0J
S" A"P
6 "ache
3ain 3emory
"orte# A%3Pcore
A, R%'-b)tb/s
A, R%'-b)tb/s
-
7/25/2019 Arm A9 Mpcore
25/25
top related