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    Carbon Nanotube Imperfection-Immune

    Digital VLSI

    H. Chen, J. Deng, A. Hazeghi, A. Lin, N. Patil, M. Shulaker, L. Wei, H. Wei, Prof. H.-S. P. Wong, J. Zhang

    Subhasish Mitra

    Robust Systems Group

    Department of EE & Department of CS

    Stanford University

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    Carbon Nanotube (CNT)

    Diameter (D) : 0.5 - 3 nm

    D

    S. Iijima

    Carbon Nanotube FET (CNFET)

    2

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    Ideal CNFET Inverter

    N+ dopedSemiconducting

    CNTs

    Gates

    Input

    P+ dopedSemiconducting

    CNTs Lithographic

    pitch

    4nm

    Sub-lithographicpitch

    Output

    Vdd

    Gnd

    3

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    CNFET Technology Milestones

    4

    1998First CNFETdemonstration[Delft, IBM]

    1998First CNFETdemonstration[Delft, IBM]

    2001Single-CNTlogic gates[IBM]

    2001Single-CNTlogic gates[IBM]

    2006Single-CNTring osc.[IBM]

    2006Single-CNTring osc.[IBM]

    2004Best single-CNTCNFET[Stanford]

    2004Best single-CNTCNFET[Stanford]

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    CNFETs: BIG Promise, BUT

    Major barriers for a decade

    Mis-positioned nanotubes

    Metallic nanotubes

    Processing alone inadequate

    Imperfection-immune

    design essential

    5

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    Wanted: (A+C) (B+D)

    Got : B+D

    Out

    A B

    C D

    Vdd

    A C

    B D

    Gnd

    Wanted: AC + BD

    Got: AC + BD + AD

    Mis-positioned CNTs Incorrect Logic

    6

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    Semiconducting CNT (s-CNT) Metallic CNT (m-CNT)

    CNFET with s-CNT CNFET with m-CNT

    Metallic CNTs

    Typical: 10 50% grown CNTs metallic

    Cu

    rrent

    Vg

    Transistor

    Vg

    Cu

    rrent

    No gate

    control

    7

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    Results

    Yesterday

    SSI single-CNT ring oscillator

    Today

    Imperfection-immune VLSI circuits

    8

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    CNFET Technology Milestones

    9

    1998First CNFETdemonstration[Delft, IBM]

    2001Single-CNTlogic gates[IBM]

    2001Single-CNTlogic gates[IBM]

    2006Single-CNTring osc.[IBM]

    2006Single-CNTring osc.[IBM]

    2004Best single-CNTCNFET[Stanford]

    2004Best single-CNTCNFET[Stanford]

    2008Mis-positioned-CNT-immuneVLSI logic gates[Stanford]

    2008FlexibleCNTcircuits[UIUC]

    2009Imperfection-immune adders& latches[Stanford]

    2009Defect-tolerantlogic gates[USC]

    2009Monolithic3D CNTcircuits[Stanford]

    2010Ultra-shortchannelCNFETs[IBM]

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    CNFET Technology Outlook

    Problem Challenge Status

    CNT alignment

    & positioning Correct function

    Metallic CNTCorrect function

    Low leakage

    CNT densityHigh current

    density

    CNT dopingComplementary

    CNFETs

    10

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    Outline

    Introduction

    Mis-positioned-CNT-immune logic Metallic-CNT-immune logic

    CNT variations

    Conclusion

    11Patil, IEEE TCAD 2008, Symp. VLSI Tech. 2008

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    1. Grow CNTs

    Mis-positioned-CNT-Immune NAND

    12

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    BA

    A

    B

    Out

    1. Grow CNTs

    2. Extended gate & contacts

    CRUCIAL

    13

    Mis-positioned-CNT-Immune NAND

    Vdd

    Gnd

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    BA

    A

    B

    Out

    1. Grow CNTs

    2. Extended gate & contacts

    3. Etch gate & CNTs

    4. Chemically dope P & N regions

    Vdd

    Gnd

    14

    Mis-positioned-CNT-Immune NAND

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    BA

    A

    B

    Out

    1. Grow CNTs

    2. Extended gate & contacts

    3. Etch gate & CNTs

    4. Chemically dope P & N regions

    Etchedregion

    ESSENTIAL

    Graph algorithms

    All possible functions

    Vdd

    Gnd

    15

    Mis-positioned-CNT-Immune NAND

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    Automated Algorithms

    Given: Layout

    Determine Mis-positioned-CNT immune ?

    16

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    Mis-positioned-CNT-Immune NAND

    17

    E

    Doped

    Doped

    Gate B

    Contact

    Doped

    Contact

    Gate A

    Doped

    Etched

    1

    1A B

    1

    1

    0

    Contact

    Contact

    B

    Contact

    Contact

    A

    GA GB

    Intended:A or B

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    Mis-positioned-CNT-Immune NAND

    18

    E

    Doped

    Doped

    Gate B

    Contact

    Doped

    Contact

    Gate A

    Doped

    Etched

    C-D-A-D-C : A

    1

    1A B

    1

    1

    0

    Contact

    Contact

    B

    Contact

    Contact

    A

    GA GB

    Intended:A or B

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    Mis-positioned-CNT-Immune NAND

    19

    Gate B

    Contact

    Doped

    Contact

    Gate A

    Doped

    Etched

    C-D-A-D-C : A

    C-D-B-D-C : B

    1

    1A B

    1

    1

    0

    B

    Contact

    Contact

    A

    E

    Doped

    Doped

    Contact

    Contact

    GA GB

    Intended:A or B

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    Mis-positioned-CNT-Immune NAND

    20

    E

    Doped

    Doped

    Gate B

    Contact

    Doped

    Contact

    Gate A

    Doped

    Etched

    C-D-A-D-C : A

    C-D-B-D-C : B

    C-D-B-D-A-D-B-D-C : A & B

    1

    1A B

    1

    1

    0

    Contact

    Contact

    B

    Contact

    Contact

    A

    GA GB

    Intended:A or B

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    Mis-positioned-CNT-Immune NAND

    21

    E

    Doped

    Doped

    Gate B

    Contact

    Doped

    Contact

    Gate A

    Doped

    Etched

    C-D-A-D-C : A

    C-D-B-D-C : B

    C-D-B-D-A-D-B-D-C : A & B

    C-D-E-D-C : 0

    1

    1A B

    1

    1

    0

    Contact

    Contact

    B

    Contact

    Contact

    A

    GA GB

    Intended:A or B

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    Mis-positioned-CNT-Immune NAND

    22

    E

    Doped

    Doped

    Gate B

    Contact

    Doped

    Contact

    Gate A

    Doped

    Etched

    Intended:A or B

    Implemented:

    A or B or

    (A & B) or 0==

    A or B

    C-D-A-D-C : A

    C-D-B-D-C : B

    C-D-B-D-A-D-B-D-C : A & B

    C-D-E-D-C : 0

    1

    1A B

    1

    1

    0

    Contact

    Contact

    B

    Contact

    Contact

    A

    GA GB

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    Automated Algorithms

    Given: Logic function

    Produce

    Mis-positioned-CNT immune layout

    23

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    Mis-positioned-CNT-Immune Layout

    24

    Gates

    Out =A + (B + C)(D + E)

    Etched regionsCNTs

    CB

    Vdd / Gnd Contact

    A

    Output Contact

    ED

    IntermediateContact

    Immune to LARGE number of mis-positioned CNTs

    Efficient

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    Most Importantly

    VLSI processing

    No die-specific customization

    VLSI design flow

    Immune library cells

    25

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    CNT Growth on Silicon Substrates

    Highly mis-positioned

    Not desirable for VLSI

    26

    10 m 4 m

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    27

    SEM image (grown CNTs)

    Quartz waferwith catalyst

    AlignedCNT growth

    99.5% CNTs aligned

    Quartz wafer

    First Wafer-Scale Aligned CNT Growth

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    28

    Silicon substrates for VLSI

    Low temperature (90oC 120oC) processing

    2 m 2 m

    Before transfer After transfer

    Target Substrate (SiO2/Si)Source Substrate (Quartz)

    Thermal ReleaseAdhesive Tape

    Wafer-Scale CNT Transfer

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    29

    First VLSI Demonstration

    10m10m10m

    Mis-positioned-CNT-immune logic gates

    NAND, NOR, AND-OR-INV, OR-AND-INV

    NOR pullup

    Etched Region

    0

    50

    100

    off

    off

    off

    on

    on

    off

    on

    on

    A

    B

    off = 2V, on = -2V

    Curren

    t(A)

    0

    0.75

    1.5

    off

    off

    off

    on

    on

    off

    on

    on

    A

    B

    off = 5V, on = -5V

    Curren

    t(A)

    NAND pullup

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    Outline

    Introduction

    Mis-positioned-CNT-immune logic

    Metallic-CNT-immune logic

    CNT variations