grid.pdf grid.pdf october 2012 · 2012-10-26 · october 2012 visit us at page 2 your networking...
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October 2012 V is i t us a t www .e-gr id .net Page 1
GRID.pdf GRID.pdf
October 2012
CHAPTER MEETINGS
SCV-Rel - 10/4 | Reliability Tour of BAE Systems - materials lab, "Bone Yard" vehicles, 25 limit ... [more]
SCV-RAS - 10/4 | Robotics for Human Exploration of Space - assisting, complicated tasks, autonomous, follow-up ... [more]
SCV-TMC+CS - 10/4 | Life Cycles for Portfolio and Program Management - stage/gate, structures, deliverables, best practice .. [more]
SCV-CS - 10/9 | Heterogeneous System Architecture (HSA): An Overview - abstract machine spec, execution, memory, languages [more]
SCV-CPMT - 10/10 | Pad Cratering, Lead Free and Density Challenges Facing Electronics Packaging - assembly temperatures, stresses [more]
SCV-ComSoc - 10/10 | Panel on Mobile Backhaul: Small Cells, LTE Challenges - solutions, players, economics, trends ... [more]
SCV+OEB-Life - 10/13 | Motivating Our Students to Become Engineers: How You Can Make It Happen - half-day forum, steps to take [more]
SCV-Nano - 10/16 | Novel Thermal Interface Materials for 3D Chip Stacks - Stanford Nanoheat Lab: tools, developments … [more]
SCV-EMB - 10/17 | Wearable Robots for Today and Tomorrow - physical limitations, exoskeleton, mobility, innovative solutions .. [more]
SCV-PELS - 10/17 | FPGA-Enabled Power Electronics Systems, Past to Present - digital control, deterministic timing, tools ... [more]
SCV-SSC - 10/18 | Accelerating Analog Design - bottlenecks, custom sizing, optimization, ease-of-use, leveraging ... [more]
OEB-IAS - 10/18 | Addressing the Grid Integration Challenges of High-Penetration Photovoltaic Systems - distributed, data ... [more]
SCV-APS - 10/18 | Antenna Synthesis: A New Way to Approach Antenna Design - AI, automatic optimization, effective solutions [more]
SCV-PES-IAS - 10/25 | Smart Grid: Opportunities for Innovation - renewable energy, infrastructure, data, analytics, reliability ... [more]
OEB-Section - 10/25 | Senior Member Advancement Mixer - upgrade to Senior Member, family night at Science Center ... [more]
SCV-CIS+SP+CAS+RAS - 10/26 | Applications of Extreme Value Theory to Signal Processing - outliers, predictions, models … [more]
SCV-Mag - 11/5 | Spin Caloritronics - physics, spin-dependent effects, dynamics, actuation ... [more]
SCV-CS - 11/14 | Crime.Com - Post-Modern Criminal Behavior - digital crime, activities, modus operandi, techniques ... [more]
SCV-CPMT - 11/14 | Cost Versus Reliability Tradeoffs for Stacked Devices - density, packaging, 3D, expenses, KGD ... [more]
OEB-Life - 11/14 | Fuel Cells, Hydrogen and the California Car Mandate - thermodynamics, H2 production, efficiency, CO2 ... [more]
OEB-IAS - 11/15 | Transformer Failure Due to Circuit Breaker Induced Switching Transients - breaker types, severity, factors [more]
SCV-CNSV - 11/16 | Solutions to the Software Patent Problem - 1-day conference, the problem, discussion of solutions ... [more]
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MARKETPLACE – Services page 3
Professional Skills Classes page 7 Career Development
Santa Clara University Grad School of Engineering Fall Open University [more]- Early-morning, evening, Saturday classes
CONFERENCE CALENDAR
Oct 7-10: Int'l Conference on Very Large Scale Integra-tion (VLSI-SoC) - Dream Inn, Santa Cruz [more]
Oct 30-Nov 1: ARM TechCon Conference and Expo - Santa Clara Convention Center [more]
Nov 4-7 : 45th Annual Asilomar Conf on Signals, Systems, and Computers - Pacific Grove [more]
Nov 4-9: IEEE International Test Conference - Disneyland Hotel, Anaheim [more]
Nov 11-15: 38th Int'l Symposium for Testing and Failure Analysis - Phoenix Convention Center [more]
Nov 27-28: Server Design Summit 2012 - Santa Clara Convention Center [more]
Dec 3-7: IEEE Global Communications Conference (GlobeCom) - Disneyland Hotel, Anaheim [more]
Dec 4-7: Printed Electronics USA Conference - Santa Clara Convention Center [more]
Dec 4-7: Android Developer Conference (AnDevCon) - Hyatt Regency Burlingame [more]
Dec 12-14: 3-D Architectures for IC Integration and Packaging - Sofitel Hotel, Redwood City [more]
Call for Papers: Int'l Symposium on Quality Electronic Design (ISQED) - March 4-6, 2013 - TechMart, Santa Clara [more] - Papers due October 12
IEEE Chapter Seminars, Workshops
Sept 29: Next Gen Circuits, Systems, Communications and Sensor Technologies in Mobile Devices One-day Seminar -- Santa Clara University [more]
Oct 11: ESD Troubleshooting Techniques for Electronic Designs; Fundamentals of Signal and Power Integrity- One-day Weekend Workshop -- Santa Clara [more]
Oct 25: Soft Error Rate (SER) Workshop- half-day free event, 10 speakers -- San Jose or streamed on Internet [more]
Oct 27: Nanovation: From Science to Startups One-day Seminar -- at UC-Berkeley [more]
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 2
Your Networking Partner ®
October 2012 • Volume 59 • Number 10
IEEE-SFBAC ©2012
IEEE GRID is the monthly newsmagazine of the San Francisco Bay Area Council of the Institute of Electrical and Electronics Engineers, Inc. As a medium for news for technologists, managers and professors, the editorial objectives of IEEE GRID are to inform readers of newsworthy IEEE activities sponsored by local IEEE units (Chapters, Affinity Groups) taking place in and around the Bay Area; to publicize locally sponsored conferences and seminars; to publish paid advertising for conferences, workshops, symposia and classes coming to the Bay Area; and advertise services provided by local firms and entrepreneurs.
IEEE GRID is published as the GRID Online Edition residing at www.e-GRID.net, in a handy printable GRID.pdf edition at the end of each month, and also as the e-GRID sent by email twice each month to more than 24,000 Bay Area members and other professionals.
Editor: Paul Wesling IEEE GRID PO Box 2110 Cupertino CA 95015-2110 Tel: 408 331-0114 / 510 500-0106 / 415 367-7323 Fax: 408 904-6997 Email: edi tor@e-gr id.net www.e-GRID.net
From the Editor
MONEY Magazine often has helpful articles about managing resources, planning your financial future, and other topics. In the last months we covered these “rules”:
Don’t wait for your company to train you.
Be an expert, not an employee.
I’d now like to focus on their third piece of advice:
Know your going rate “When its time to negotiate salaries and raises, use compensation sites like PayScale, GlassDoor.com, and Vault.com [and IEEE’s salary survey] to figure out what pay range is appropriate for what you do. Then negotiate from the upper end of that range.”
Finding out what others are getting paid for the same job is uncomfortably difficult. These suggestions should let you find what you’re worth, or at least get you in the ballpark. And in Silicon Valley, where moving between companies is notoriously easy, you may find that checking on potential openings with hiring managers at similar companies can be done at local IEEE chapter meetings.
First, determine which other Valley companies would be using a skillset like yours. Then, watch for attendees from these companies (many Chapters issue name/company badges to attendees, to promote discussions). Finally, see if this person has salary-level information and might be willing to share. It doesn’t hurt to show your interest!
Best regards,
Paul
NOTE: This PDF version of the IEEE GRID – the GRID.pdf – is a monthly publication and is issued a few days before the first of the month. It is not updated after that. Please refer to the Online edition and Interactive Calendar for the latest information.
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OFFICERS Chair: Shirin Tabatabai
Secretary: Ed Aoki/Brian Berg Treasurer: Brad McHale
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October 2012 V i s i t us a t w w w . e - G R I D . n e t Page 3
Patent Agent Jay Chesavage, PE
MSEE Stanford 3833 Middlefield Road, Palo Alto 94303
www.File-EE-Patents.com TEL: 650-619-5270 FAX: 650-494-3835
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MET Laboratories
EMC – Product Safety
US & Canada
• Electromagnetic Compatibility • Product Safety Cert. • Environmental Simulation • Full TCB Services • Design Consultations • MIL-STD testing • NEBS (Verizon ITL & FOC) • Telecom • Wireless, RFID (DASH7 & EPCglobal Test Lab)
Facilities in Union City and Santa Clara
www.metlabs.com [email protected] 510-489-6300
IEEE-CNSV Consultants' Network
of Silicon Valley
• Become a member • Find a Consultant • Submit a Project
CaliforniaConsultants.org
• Patent application preparation, prosecution, IP Strategy • Enforcing, Licensing and Monetizing Patents • Broad Experience in many Electrical and Software arts • Our Experts: IEEE Fellow, SPIE Fellow, Technical and Legal Experts
Ph: 408-288-7588 www.StevensLawGroup.com
Email: [email protected]
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Channel Partner
Multiphysics, Multidisciplinary Engng CFD, Stress, Heat Transfer, Fracture Fatigue, Creep, Electromagnetics Linear/Nonlinear Finite Element Analyses Multi-objective Design Optimization BGA Reliability
Ozen Engineering (408) 732-4665
[email protected] www.ozeninc.com
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 4
Come explore the state-of-the-art and new developments in Very Large Scale Integration (VLSI), System-on-Chip (SoC) and their designs – a forum to exchange ideas and show industrial and research results in the fields of VLSI/ULSI Systems, SoC design, VLSI CAD and Microelectronic Design and Test.
Topics include: ● Analog and Mixed-Signal IC design ● Microsystems and integrated MEMS for bio-systems ● Design for variability, reliability, fault tolerance, test ● Circuits and systems for DSP, image processing, communications ● Emerging technologies and new devices ● Prototyping, verification, silicon debug for SoCs ● 2D- and 3D-interconnect architectures, topologies ● System-on-chip, embedded VLSI systems, multi-core systems ● Reconfigurable systems, application-specific processors, FPGAs ● Digital VLSI circuits, memories ● Logic and high-level synthesis, SW synthesis, HW-SW co-design ● Low-Power and Temperature-Aware design
The Asilomar Conference on Signals, Systems, and Computers is a forum for presenting work in various areas of theoretical and applied signal processing.
75 Sessions, including: ● Graphical Models in Signal Processing ● Green Radio ● Voice Coding ● Full-Duplex MIMO Communications ● DSP Architecture for Wireless Communications ● Large-Scale MIMO Systems ● Compressive Sensing ● Network Beamforming ● Cognitive Radio Networks ● Many-Core, Multi-Core, and SoC ● Image and Video Coding ● Computer Arithmetic ● Wireless Video Transmission ● Game Theory in Communications ● Medical Image Analysis ● Coding Theory for the Next-Gen Storage Systems ● Compressive Estimation ● Multiuser and Massive MIMO ● Social Networks ● Sequence and Genome Analysis ● Low Power ● Network Optimization ● Security ● Consensus Based Algorithms ● Wireless Full Duplex ● Decoding and Detection ● Interference Alignment ● Image and Video Classification … and more
International Conference on Very Large Scale Integration
(VLSI-SoC)
October 7-10, 2012 Ocean-Front: Dream Inn, Santa Cruz
Registration is still open …
More infromation at
vlsisoc2012.soe.ucsc.edu
Special Sessions
Memristive Computing Memristors and memristive devices have recently been realized at nanoscale. Several recent implementations have brought forth the potential for revolutions in non-volatile storage and reconfigurable computing. This special session is specifically focused at using memristive devices for computing in programmable systems such as FPGAs.
Open Source Tools and Methodologies for Research Open source tools enable both academia and industry to research, develop, and share common platforms in complex research tasks. However, most often these open source tools and methodologies are unsung and, in fact, difficult to publish. This special session is specifically focused on recognizing the most important and useful open source tools and methodologies that aid research.
ASILOMAR CONFERENCE GROUNDS
PACIFIC GROVE
November 4-7, 2012 2012 Plenary Talk: “Compressive Sensing: 8 Years After,” Prof. Richard G. Baraniuk, Rice University
Half-Day Tutorial: “Coding Methods for Emerging Storage Systems” – Prof. Lara Dolecek, UCLA, and Prof. Anxiao (Andrew) Jiang, Texas A&M
Save $250 through Oct. 15th.
For more information, and to register, visit:
www.asilomarssc.org
Asilomar Conference on Signals,Systems, and Computers
CALL FOR PAPERS ISQED 2013
14th International Symposium on
QUALITY ELECTRONIC DESIGN
March 4-6 , 2013
Techmart Center, Santa Clara, CA, USA www.isqed.org
Paper Submission Deadline: Oct. 12, 2012 Acceptance Notifications: November 24, 2012 Final Camera-Ready paper: January 10, 2013
A pioneer and leading multidisciplinary conference, ISQED accepts and promotes papers in following areas: Papers are requested in the following areas:
System-level Design, Methodologies & Tools FPGA Architecture, Design, and CAD Design of Embedded Systems Advanced 3D ICs & 3D Packaging, and Co-Design Robust & Power-conscious Circuits & Systems Emerging/Innovative Device Technologies and Design Issues Design of Reliable Circuits and Systems
IP Design, quality, interoperability and reuse Design Verification and Design for Testability Physical Design, Methodologies & Tools EDA Methodologies, Tools, Flows Design for Manufacturability/Yield & Quality Effects of Technology on IC Design, Performance, Reliability, and Yield
The guidelines for the final paper format are provided on the conference web site. Paper submission must be done on-line through the conference web site at www.isqed.org. In case of any problems email [email protected]. ISQED papers are published in IEEE Xplore.
Submission of Papers
CALL FOR PAPERS
IEDEC 2013 Interdisciplinary
Engineering Education Conference
March 4-5 , 2013 Techmart Center, Santa Clara, CA, USA
www.iedec.org
Abstract Submission Deadline: Oct. 12, 2012 Acceptance Notifications: November 24, 2012 Final Camera-Ready paper: January 10, 2013
IEDEC accepts and promotes papers in following areas: Papers are requested in the following areas:
• Latest Educational Hardware and Software Tools and Techniques • Advanced and Innovative Design Automation Tools • Exploring the Increasing Role of Engineering in our Life • Promoting Innovation and Creativity in Engineering Design • Management of Design • Trends in Engineering Education • International and Global Aspects of Engineering Education • Student Projects and Internships
• Learning Environments, Tools, and eLearning • Combining Teaching and Research • E-learning and E-assessment, • Continuing Education & Its Delivery • Collaboration Between Universities, Industry, and Government • Engineering Education & Women • Distance Learning and Distance Teaching • Engineering Education Outreach
The guidelines for the final paper format are provided on the conference web site. Paper submission must be done on-line through the conference web site at www.iedec.org. In case of any problems email
Submission of Papers
[email protected]. IEDEC papers are published in IEEE Xplore.
September 2012 Visit us at www.e-GR I D.net Page 5
September 2012 V is i t us at
www. is t fa .org 9 egaP ten.DIRG-e.www
CONFERENCESunday-Thursday, Nov. 11-15
Sunday: Tutorials
Monday-Thursday: Technical Programming with Intermixed Tutorials
ENRICH YOUR CAREER AND FURTHER THE INDUSTRY AT THE 38TH INTERNATIONAL SYMPOSIUM FOR TESTING AND FAILURE ANALYSIS (ISTFA), NOVEMBER 11-15 IN PHOENIX, ARIZONA.ISTFA™ is the best venue for learning new failure analysis techniques, solutions and enterprise for success.
Acquire the latest knowledge from the field's leading professionals with intermixed tutorials, short courses, technical presentations, panels, and user groups. Research leading-edge instruments and solutions at the industry's largest dedicated equipment exposition. Meet and network with hundreds of your peers from around the world. All this makes ISTFA your best opportunity to learn, network and advance your career.
Register before October 1 for early bird specials.Go to www.istfa.org for up-to-date information and to register.
NEW INTERMIXED TUTORIAL FORMAT A full day of tutorial sessions Sunday with cutting edge topics related to current trends in failure analysis intermixed throughout the week.
• Lab Management • Fault Localization• Electrical and Yield • Microscopy• Technology Specific FA • FIB• Package and Physical Analysis Challenges
23 TECHNICAL SESSIONS INCLUDING PANEL DISCUSSION: FA CHALLENGES OF 3D INTEGRATION• Emerging Concepts and Techniques• Fault Isolation and Failure Analysis of 3D Packages• Nanoprobing Techniques/Applications• Fault Isolation and Failure Analysis of TSVs• Photon Based Techniques: An Understanding• Rethinking the FA Process• Improving Fault Isolation with Software• Packaging and Assembly Analysis• Counterfeit Electronics Detection and Mitigation• Circuit Edit: Beam Interaction Studies, Strategies• TEM Defect Detection • Device Level Sample Prep• Chip Level Sample Prep • Alternative Energy• Case Studies • Defect Analysis• Test and Diagnosis • Posters
NETWORKING AND SOCIAL EVENTS• Attendee Luncheons• Networking Reception• Tools of the Trade Tour - Registration is required• Hitting a Home Run with your Failure Analysis – Inside the Diamondbacks’ Chase Field• Dessert Reception and Poster Session
TECHNOLOGY-SPECIFIC USER GROUPSMeet, share ideas, and discuss relevant issues in a noncommercial environment. Planned topics are:
• Nanoprobing • Contactless Fault Isolation• Focused Ion Beam • Sample Preparation
EDUCATION SHORT COURSES 7 Pre- and Post-Conference Short Courses
• NEW! Photovoltaic Modules: Reliability and Test Standards• Fault Isolation• Counterfeit Electronic• NEW! Failure Analyzing the Failure Analysis Process• NEW! Electrostatic Discharge in Robotic Manufacturing Lines: Electrostatic Basics, ESD-Failure Mechanisms, Tool Risk Evaluation Methods and ESD- vs. EOS-Classification and Characterization Methods• NEW! ESD/ Factory EOS• Financial Management of the FA Process
2012 KEYNOTE ADDRESS University Innovation: How Today’s Academic Research Seeds Tomorrow’s Commercial Breakthroughs
Trevor J. Thorton, PhD, Professor and Director of Electrical Engineering, Arizona State UniversityHear first-hand the trials and tribulations faced by researchers on the road towards commercial breakthrough.
REGISTER BY OCTOBER 1 AND SAVE.• Discounted fees for EDFAS and ASM Members. • Non-members of EDFAS receive a one year membership with their registration.• Group discounts available
Additional information is on the ISTFA website.
Plan and register at www.ISTFA.org.
EXPOSITION - NOV. 13-14The ISTFA exposition is North America’s largest tradeshow of FA-related equipment and services. This promises to be an exciting year on the show floor where you will see the latest industry advances and network with vendors for problem-solving advice. Bring your questions, needs and concerns. Get solutions to your FA problems!
NEW in 2012!• Tools of the Trade Tour – See the latest products and services in action• Photo Contest• Networking Reception on the show floor• “Video Street Beat” – Coverage of your booth by editors of AM&P and EDFA magazines
The ISTFA exposition is your once-a-year opportunity to access the innovators, influencers, and decision makers –all in one location!
To exhibit, sponsor or advertise, contact Kelly Thomas at [email protected] or 440.338.1733.
October 6
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 7
Communicating Across Cultures
– Thurs, October 11, 9:00AM-5:00PM – Location: TIBCO Software, Palo Alto – Fee: $400 for IEEE Members; $500 non-members
A “must” if you collaborate in a global team, serve customers/suppliers abroad, or work with culturally diverse H1B professionals.
Transitioning from Individual Contributor to Manager
– Date/Time: Thursday, Oct 18, 9:00AM-5:00PM – Location: TIBCO Software, Palo Alto – Fee: $425 for IEEE Members; $525 non-members "Excellent! The instructor's experiences have clearly demonstrated direction and path I would like to experiment. This class was very clear and concise"
Project Management: A Team Approach for Accountability & Results
– Date/Time: Mon-Tues, Oct 22-23, 9:00AM-5:00PM – Location: TIBCO Software, Palo Alto – Fee: $650 for IEEE Members; $725 non-members
December 4-7, 2012 Santa Clara Convention Center
The ninth annual Printed Electronics USA conference and exhibition covers all the applications, technologies and opportunities.
Printed Electronics USA gives the big picture, not least by inviting leading speakers from around the world from a range of industries including consumer goods, healthcare, military, electronics, advertising, publishing and others. Commercialization and the full range of technologies are the emphasis, from interactive packaging and promotional posters to sensing fabrics and ultra low cost wireless identification tags.
Photovoltaics USA covers the solar cell sector. All the latest developments in thin film, organic, printed photovoltaics as well as emerging technologies growing alongside the more established ones, such as luminescent concentrators and infrared harvesting.
Graphene LIVE! covers all promising applications of graphene, including graphene composites, batteries and supercapacitors, functional inks, logic and memory, touch screens, sensors and bio-electronics and beyond.
SCV Chapters, Technology Management & Components, Packaging and Manufacturing Technology Societies
Managing Time & Multiple Priorities – Date/Time: Tuesday, Oct 30, 9:00AM-1:00PM – Instructor: Peter Turla – Location: Synopsys, Sunnyvale – Fee: $325 for IEEE Members; $375 non-members "I enjoyed this class very much. I thought it was very informative and useful. It really made me more aware of how I can organize my time."
Emotional Intelligence -- Date/Time: Thursday, Nov 1, 9:00 AM – 5:00 PM -- Location: – Tibco, Palo Alto -- Fee: $450 for IEEE Members; $525- non-members
“Emotional intelligence isn't a luxury you can dispense with in tough times. It's a basic tool that, deployed with finesse, is a key
to professional success.” --- Harvard Business Review.
Upgrade your skill set – prepare for future challenges
For complete course information, schedule, and registration form, see our website:
www.EffectiveTraining.com*
The world's most comprehensive event on printed, organic and
flexible electronics
Master Classes on Dec 4, 7 • Intro to Printed, Organic and Flexible Electronics • Thin Film Photovoltaics • Displays & Lighting • Printing Technologies • Graphene and Carbon Nanotubes • Organic and Inorganic Functional Materials • Creating New Products with Printed Electronics • Flexible Substrates, Barriers and Transparent Films • RFID & its Progress Towards Being Printed • Energy Harvesting & Storage for Small Electronic Devices
Use code “IEEE25” for 25% discount thru Dec.1. Exhibits-only option available.
www.PrintedElectronicsUSA.com
Exhibit at the Tradeshow! Over 100 leading companies will be showcasing innovative technologies and commercial applications in the field of printed electronics and photovoltaics at the world’s biggest tradeshow on the topic – an ideal place to meet your potential customers. For information on exhibiting, please contact Tom Keenan, [email protected]
IEEE Professional Skills Courses
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 8
Immerse yourself in Best-in-Class design strategies for leading embedded architecture - ARM
This year's ARM Techcon doubles your value
with two events in one. Whether you are a hardware or software engineer, ARM Techcon 2012 offers classes, hands-on tutorials and training at all levels of expertise. Invest in your in future today with a solid core of strategies, tools and methodologies for successfully incorporating ARM IP in your design. Choose to attend October 30th where the focus is on designing ICs using ARM cores, or October 31 -November 1, where the focus will be on designing systems and developing software around ARM-based hardware. If your responsibilities span across both areas- we offer an all-access pass to attend the entire conference, the best value – plus there’s an IEEE discount. The exhibition floor is unique, based on which days you attend.
Get the Solutions for your ARM-Powered Designs
Keynote Talks Simon Segars, EVP and General Manager Processor and Physical IP Divisions, ARM Jack Sun, VP, Research & Development and CTO, TSMC Jonathan Koomey, Stanford University Warren East, CEO, ARM
ABOUT ARM ARM designs the technology that lies at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM's comprehensive product offering includes 32-bit RISC microprocessors, graphics processors, enabling software, cell libraries, embedded memories, high-speed connectivity products, peripherals and development tools. Combined with comprehensive design services, training, support and maintenance, and the company's broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies.
Exhibit at ARMTechCon6! Don’t miss this opportunity to showcase your ARM-based products or technology solutions. Increase ROI, launch new products, influence target customers, expand your visibility. Contact Seam Raman, Sales Director, [email protected], 415-947-6622.
CHIP DESIGN DAY (October 30)
A one-day intensive conference for chip design teams working with ARM silicon IP and tools.
110 papers - Tracks on: - SoC Architecture & Analysis - SoC Design & Verification - SoC Design for Power & Performance - SoC IP Sponsors:
SYSTEM AND SOFTWARE DESIGN DAYS (October 31 – November 1) Two days of courses and exhibits for system developers employing the ARM architectures.
Tracks on: - Android/Open Source - Compute Platforms - Developing & Debugging - Low Power Design - Microcontroller and Programmable Platforms - Multimedia Processing - Safety & Security - Software Optimization on ARM-Powered systems - The Fundamentals of ARM Sponsors:
Register by October 29 to Save $200
Get an extra 20% discount with code “GRID”
Register today:
e.ubmelectronics.com/armtechcon A free Exhibition-Only pass includes access to the exhibits, keynotes, industry addresses, sponsored technical sessions, teardowns, and opening-night reception..
Oct. 30 –Nov. 1, 2012 Santa Clara Convention Center
- Chip Design Day - System & Software Design Days
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 9
Building the Lean, Green Super Machine
Server Design Summit is the only event focused entirely on the $40 billion server market. And it is the first event to deal with “Bringing Servers into the Cloud Computing Era.”
This two-day event will bring you the latest in designing for next-generation virtualized servers! From simple blades to powerful high-end systems, servers are the key to managing networked computing. Talk with industry leaders, see the latest products, meet with potential partners. Organized in three tracks:
Saving Energy in Servers and Datacenters
Increasing Server Performance
Designing Cloud Servers Special Sessions “Facebook Open Compute Project,” Amir Michael, Facebook
“VC Forum,” with Battery Ventures, US Venture Partners, Lightspeed Venture Partners, NEA
Panel on "Cloud Server Design Tradeoffs" with panelists from Dell, HP, SeaMicro, Cisco Systems and Oracle
Panel on "Future of Server Design" with panelists from Calxeda, Intel, Oracle and IBM Almaden Research Center
Evening Discussion Tables Beer, Pizza and Chat with the Experts Table Topics: • Cooling methods • High-speed links • Storage performance • Memory • Virtualization • Security • Application acceleration • Server accelerators • Caching methods • Cloud servers • Marketing • Backup and recovery
Shipments of cloud servers are projected to reach 875,000 units in 2012, up a notable 35 percent from 647,000 in 2011 and nearly double the 460,000 in 2010. — Peter Lin, IHS ISuppli, January 2012
Keynote Speakers “Cloud Computing and the Mega-Datacenter,” Jason Waxman, General Manager, High Density Computing Data Center Group, Intel Corporation
"Servers Meet Today's Enterprise Information Challenges," Robert Hormuth, Director, Server Architecture, Dell
"Cloud-Scale Networking - The Evolving Network Edge," Sarwar Raza, Distinguished Architect, Hewlett-Packard
"Getting Big Results from Big Data," Keith Klemba, Vice President, SAP Research
"Solid State Memory Increases Server Performance Cost-Effectively," Adam Roberts, Solid State Memory Architect & Senior Engineer, IBM Sessions and Panels: - CPU Data Demands - Optimizing Cloud Servers for Cost and Performance - System Power Management - Increasing Storage Performance - Accelerating Cloud Connectivity - Data Center Server Strategies - System Scaling and Networking - Virtualization and Cloud Servers - Accelerating Application Performance - Cloud Server Design Tradeoffs - Future of Server Design ... and more!
Review the full program on the website
Save $300 through November 21st. Save an additional $100 with code "IEEE"
For more information:
www.serverdesignsummit.com
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 10
Today the focus on 3-D integration and packaging
has shifted from trying to understand the technology opportunity to one of understanding the practical challenges of technology adoption and commercialization, including who is getting there first, how, and at what cost. There remains a natural degree of uncertainty as companies work to secure a technology position, obtain new process and design tools, and new customers and new applications.
This conference continues to give a broad, yet thorough perspective on the techno-market opportunity and challenge offered by building devices and systems in the vertical dimension. Industry leaders from around the world are invited to speak on topics important to the emerging and on-going 3-D related efforts. The format of the conference and its presentations enables speakers to present the most up-to-date and forthright perspectives as possible. This conference provides a unique forum where one can gain the latest insights to bring clarity in the direction of their own efforts.
Have you ever wanted to continue your education in engineering while you continued working? Santa Clara University’s School of Engineering offers graduate degree and non-degree programs to both full-time students and working professionals. Simplified registration for the Spring Open University. Graduate-level instruction. Up to 16 units may be transferred to a graduate-degree program.
Early-morning classes: - Linear Algebra - Speech Coding - Applied Math - Intro to Systems Engineering (and more)
Evening classes: - Web Architecture & Protocols - Logic Design Using HDL - IC Fab Processes - Nanoelectronics (and more)
Saturday classes: - Wireless Mobile Networks - Design of SOCs - Law, Technology, IP (and more)
Email LeAnn Marchewka with inquiries: [email protected]
Monday Pre-Conference Half-day Symposium: “3-D ICs and TSVs—Passing the Test”
- Automation of DFT - Process Control Solutions - Metrology and Standards - TSV Array Macro-inspection
Sessions: 3-D Integration: Shaping the Future Techno-Market Views on the 3-D Era 3-D Design and Interposers 3-D Integration: Shaping the Future Application and User Perspectives Leading Consortia and Sponsored Research Efforts Tooling and Processes Hold the Key
Earlybird Rates through October 31st (save $150). Corporate multi-attendee discount.
Full details:
techventure.rti.org Prepare for that next
project or assignment!
To remain competitive in Silicon Valley's changing environment, engineers need to update their knowledge base. The School of Engineering offers professional Certificates and Open University programs, as well as graduate degrees, for those who are driven to become leaders in their fields.
Registration opens October 20 Classes begin January 7
Located in the heart of Silicon Valley, with easy parking
Review winter Open University courses:
www.scu.edu/engineering/graduate
Sofitel Hotel, Redwood City December 12-14, 2012
Santa Clara University School of Engineering Graduate Programs
SCU Winter Open University
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 11
IEEE GLOBECOM is the Premier Event for telecommunications industry professionals and academics from companies, governmental agencies and universities around the world, with a technical program focused on recent communication research and development. GLOBECOM includes 12 symposia conducted by the various ComSoc technical committees covering major industry technologies and numerous hot topics – over 1000 presentations.
Keynote Presentations: - Vint Cerf, Google: “Internet Challenges 2012-2020” - Henry Samueli, CTO, Chairman, Broadcom - Krish Prabhu, President, AT&T Labs, CTO, AT&T - Hossein Eslambolchi, “The Power of Technology to
Transform the Future”
Technical Sessions over 160 sessions across 12 Symposia tracks, including sessions on:
● Green Hardware and Chip Designs ● Energy Saving in Communication Network and Equipment ● Multimedia Quality of Service ● Compressed Sensing ● Theoretical Aspects of Communication Systems ● Femto-Cell Networks ● Network Coding ● Security in Cloud Computing and Storage ● Network Layer Modeling and Design ● Optical Spectrum Management ● Cognitive Radios Networks ● Spectrum Sharing ● Interference Management ● MIMO Systems ● Satellite & Space Communications ● Traffic Control ● Network Design and Management ● … and many more – see Program!
Technical Tutorials Twelve half-day tutorials ● Intro to Small Cell Wireless Networks ● Mobile-Station and Base-Station Cooperation ● Interference Alignment ● Gigabit Wireless LAN (IEEE 802.11ac) ● Content Delivery Acceleration ● QoS Provisioning in Wireless Cognitive Radio Network ● M2M in Smart Grid & Smart Cities ● Resource Management in Mobile Cloud Computing ● Opportunistic Communication ● Security Investigation on 4G LTE Wireless Networks ● Cooperative Spectrum Sensing: From Fundamental Limits to Practical Designs ● Joint PHY-MAC Design for Spectral- and Energy-Efficient Wireless Networks
22 Full-Day Workshops selection: ● Heterogeneous and Small-Cell Networks ● Smart Devices ● Broadband Wireless Access ● Green Internet of Things ● Machine-to-Machine Communications ● Unmanned Autonomous Vehicles ● Radar and Sonar Networks ● Wireless Cloud Computing ● Multicell Cooperation ● Optical Wireless Communications … and more
Theme: “The Magic of Global Connectivity”
GLOBECOM INDUSTRY FORUM & EXPO – FOR WORKING ENGINEERS!
GLOBECOM, features an exposition of key providers of technology and tools, including Components, Subsystems and Systems, Test Equipment, Hardware, Software, and Middleware. The Industry Forum includes a Welcome Reception and twelve 2-hour forum sessions with broad interest programming, focused on the telecommunication industry’s current practiced technology, major technology implementations, complex IT business systems, regulatory impact assessments, economic models, and engineering methods used by industry practitioners. Disneyland Hotel
The Disneyland Resort Hotel is located steps away from the Disneyland and California Adventure parks. It is packed with fabulous dining and unexpected delights. At select times, Disney Characters are available to meet and greet Guests in the Disneyland Hotel main lobby. Bring your family! Register for your hotel room by November 2, to assure our conference rates.
GLOBECOM Early Registration Deadline:
November 2, 2012 – Save $125! For Advance Program and registration information:
www.IEEE-GLOBECOM.org
To exhibit at GLOBECOM this year, in Anaheim, please contact Frank Chang, Tel: 1-805-218-9796, or email:
December 3-7, 2012 Disneyland Hotel, Anaheim
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 12
AnDevCon Comes Back to Burlingame!
AnDevCon IV is the technical conference for software developers building or selling Android apps. Whether you're an enterprise developer, work for a commercial software company, or are driving your own start-up, if you are building Android apps, you need to attend AnDevCon. You’ll find hundreds of experienced developers and engineers (like you) choosing from more than 50 classes to bring Android open source development to a high level. Exhibit Hall hours:
Thursday Dec 6, 11:00 am – 7:00 pm Friday Dec 7, 11:00 am – 2:30 pm
“This was a great conference! The scope and breadth of
classes gave a great opportunity to learn more about Android development in general AND gave the
opportunity to network with other people at all levels. It's a great learning place with wonderful people!”
Andrew Mauer, Sr. Project Manager, B-Line Express, Inc.
The 4th annual IEEE Santa Clara Valley SER workshop provides a unique forum for component manufacturers, assembly houses, and electronic system manufacturers to exchange innovative ideas and recent results on the measurement, monitoring, and control of alpha emission from packaging materials and manufacturing processes. Built on the success of our workshops held in 2009 through 2011, this year’s event will continue to cover a wide range of areas and subjects critical to the control of device soft error rates. Most talks have been selected; see the website for full program.
December 4-7, 2012 Hyatt Regency Burlingame
Technical Classes Keynotes, Exhibits, more
Keynotes: Chet Haase, Android Team, Google Roman Guy, Software Engineer, Google
Technical Classes: - Android Fundamentals - Attacking Android Insecurity - Developer Tool Essentials - Hacking APKs for Fun and Profit - Architecting Android Apps - Creating Apps for Google TV - Advanced OpenGL ES - Mastering the Android Touch System - Leveraging Android's Linux Heritage - Mobile Data Synchronization - Reusable Custom Components - Utilizing Sensors in Android - Creating ePub Books for Android - Extending the Android Vibrate Function for Games - Tracking User Behavior … plus dozens more, and choice of 7 Workshops
Earlybird registration thru October 19 – save $500 And save $100 by using Code “IEEE”
on 3-day passport, or for free exhibits admission.
For information and to register, visit
www.AnDevCon.com
Speakers: • Nelson Tam, Marvell; • Robin Gardiner, Matheson Gas; • Bharat Bhuva, Vanderbilt University; • Jeff Wilkinson, Medtronic; • Brendan McNally, XIA; • Mike Gordon, IBM; • Shah Jahinuzzaman, Intel; • Brett Clark, Honeywell; • Yi-Pin Fang, TSMC; • Sang H. Baeg, Hanyang Univ.
No charge for Workshop (includes light lunch)
Held at Cisco Systems, 3750 Cisco Way, San Jose
Also broadcast LIVE on the Internet, via WebEx More information and to register:
www.cpmt.org/scv
Access last year’s talks as webcasts, from the Chapter website.
CPMT, EDS and Reliability Chapters
Soft Error Rate (SER) Workshop Thursday October 25, 2012 – at Cisco Systems, San Jose
Registration and lunch at 11:00 AM Talks from 11:30 – 5:00 PM
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 13
Weekend Workshop: Next Generation Circuits & Systems,
Communications and Sensor Technologies in Mobile Devices
Speakers: Prof. Tom Lee, Stanford; Prof. Roger
Howe, Stanford; Prof. Viktor Gruev, Washington U; Theodore Yu, TI; Prof. Debbie Senesky, Stanford; Steve Lloyd, InvenSense; Jay Esfandyari, STMicroelectronics; Harmeet Bhugra, IDT
Time: 8:30 AM to 4:45 PM Cost: $30 for IEEE members, $40 for others
(includes lunch -- $10 more after Sept. 22) Place: Edward J. Daly Science Center, Santa
Clara University, Santa Clara RSVP: from website Web: ewh.ieee.org/r6/scv/comsoc or
ewh.ieee.org/r6/scv/cas High Resolution and Real-Time Polarization Imaging Sensors by Viktor Gruev, Department of Computer Science and Engineering, Washington University in St. Louis, St. Louis, MO.
Solid state imaging devices now dominate the multi-billion dollar industry of digital photography. These typically capture two properties of light, namely the intensity and the wavelength, and encode this information into perceptual quantities of brightness and color. The third property of light, polarization, has been ignored by solid state imaging sensors partially due to the human inability to discriminate polarization information.
In this talk Prof. Gruev will present a novel imaging sensor capable of capturing the polarization properties of partially polarized light in high resolution and in real-time. The imaging sensor monolithically integrates aluminum nanowire optical filters with CCD imaging array to achieve a high resolution polarization imaging sensor.
Prof. Gruev will also present several applications that take advantage of the high resolution and real-time sensing of polarization information. These applications range from underwater imaging of polarization phenomena in marine species, to tracking of vehicles in urban environment and endoscopic imaging of mouse heart tissue.
(continued, next page )
This workshop covers advances in MEMs based sensors and the continuing progress in the integration of these sensors with control, signal processing and communication electronics. Several of the speakers will also address end-user solutions (motion characterization, contextual awareness, gestures, sensor-aided navigation, haptic feedback, health and fitness, life-logging, etc.) which illustrate what can be achieved with the availability of these sensing interfaces (Accelerometer, Proximity, Touch, Pressure, Camera etc) on a connected platform.
After a keynote talk by Professor Tom Lee, we will have two themes. The first (morning) theme focuses on progress in the development of circuits, sensors and devices whereas the second (afternoon) theme covers advances in hardware and identifies applications/usage scenarios. Each session is approximately 2 hours and 30min duration including keynotes and Q&A. The attendees will also have an opportunity to interact with vendors at the tabletop exhibits. There will also be an opportunity to review projects from Santa Clara University’s Center for Science, Technology, & Society at this workshop. Workshop Speakers: Keynote: Prof. Tom Lee, Stanford University Morning: Progress in Circuits, Sensors & Devices Morning Keynote: Prof. Roger Howe, Stanford Speaker 1: Prof. Viktor Gruev, Washington Univ Speaker 2: Theodore Yu, Texas Instruments Speaker 3: Prof. Debbie Senesky, Stanford
Lunch & Networking
Afternoon: Hardware & Applications Afternoon Keynote: Steve Lloyd, VP of Engineering,
InvenSense Speaker 1: Jay Esfandyari, MEMS Market
Development Manager, STMicroelectronics Speaker 2: Harmeet Bhugra, Managing Director,
MEMS Group, IDT Inc. Speaker 3: Being confirmed.
SATURDAY September 29, 2012
SCV Communications, with Circuits and Systems
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 14
Event-based Analog Sensing by Theodore Yu, PhD, Texas Instruments
The event-based sensing approach encodes features of interest from the environment or scene into events. Incorporation of low-power analog signal processing locally near the sensor seeks to reduce the amount of redundant data processed in the system. Furthermore, encoding of relevant features into time-stamped events allows for additional signal processing techniques that naturally exploit the temporal dynamics of the sensed information. Dr. Yu will first present some work that implements event-based sensing techniques for visual and acoustic sensors. The second part, he will cover the design and implementation of an event-based processor modeled after the dynamics of the brain. Within this architecture Dr. Yu will demonstrate spike-based event-driven coincidence detection in neural synchrony with applications towards temporal encoding and decoding of scenes.
Progress in Extreme Environmental Sensing Using Wide Bandgap Semiconductor Thin Films by Prof. Debbie G. Senesky, Stanford University
In this presentation, Prof. Senesky will discuss the synthesis of temperature tolerant, chemically resistant, and radiation-hardened wide bandgap semiconductor thin films and nanostructures. These new material sets serve as a platform for the realization of sensor, actuator, and electronic components that can operate and collect data under the most hostile conditions. More specifically, smart and adaptable structures for extreme environments are enabled through the technology developed in her laboratory. Her research efforts support a variety of applications including deep space systems, hypersonic aircrafts, combustion monitoring and subsurface monitoring.
Track-2 Keynote: CMOS-MEMS Integration will be a Requirement for the Next Generation “Smart” MEMS Sensors by Stephen Lloyd, VP of Engineering, InvenSense
In years past, many of the attempts at CMOS-MEMS integration have had marginal results. Consequently, many of today’s leading high volume MEMS suppliers use separate MEMS and CMOS processes and leverage advanced packaging to combine the two die into a single package. There are significant challenges in combining MEMS with CMOS, yet once these challenges are overcome, a CMOS-MEMS platform offers a significant advantage for implementing highly integrated “smart” sensors. Verified by the evolution of CMOS technology, integration is an extremely powerful tool to lower overall solution cost and power. CMOS-MEMS integration achieves similar significant advantages in
cost, size, and power consumption over solutions with separate MEMS and CMOS. This discussion will cover the challenges of CMOS-MEMS integration and demonstrate how effective solutions to these challenges exist and are in high-volume production today. We will discuss the advantages of a CMOS-MEMS platform for many applications such as inertial, audio, ultra-sonic, timing, RF, biological, chemical and gas sensing. The talk will also briefly cover a CMOS-MEMS platform that is available via a fabless design model (NF Shuttle) where silicon is manufactured at leading foundries.
Emerging Multi-sensor Modules and Sensor Fusion Enables New Applications by Jay Esfandyari, MEMS Market Development Manager, STMicroelectronics
MEMS based sensors hold a distinct edge over other technologies in performance, size, cost and current consumption. These advantages have enabled the strong penetration of MEMS sensors into high growth applications in portable devices.
Multi-sensor based applications such as indoor navigation, motion gaming, robot balancing, image stabilization, air mouse, human body tracking and unmanned aerial vehicles, etc. require the fusion of the data of these sensors to achieve high performance and short response time.
This presentation will give an overview of which sensors are used in sensor fusion, what the major technical parameters are required and what the most popular applications of the sensor fusion solution are. It will also discuss the challenges the developers are facing and the limitations associated with the sensor fusion implementation.
Introducing World’s first Piezoelectric MEMS Oscillators by Harmeet Bhugra, Managing Director, MEMS Group, Integrated Device Technology, Inc.
Mr. Bhugra will discuss the introduction of world’s first high performance piezoelectric MEMS oscillators. These non-quartz oscillators are gradually penetrating the $4B frequency reference marketplace and are increasingly being favored by system designers. He will discuss major application trends and address why alternative solutions to quartz are gaining traction. He will also discuss what it takes to get a MEMS product from paper to production including key lessons learned during development.
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 15
Reliability Tour of BAE Systems
Speakers: BAE Staff Time: 5:00 PM to 7:00 PM (arrive at 4:45 PM) Cost: none Place: BAE Systems, 1205 Coleman, Santa Clara
(visitor parking spaces out front; alternate is across Brokaw)
RSVP: by email to Mike Silverman, [email protected] -- first 25 only.
Web: ewh.ieee.org/r6/scv/rl
This tour is being extended to us and is special. It
is a "Public Domain" tour. What they will see -
- Materials Lab - Tour of the "Bone Yard" - many vehicles of different ages - There are other areas that we are working
to get into. We need to respectful of all rules and limitations.
Be aware, by entering the facility, you are accepting that you and your possessions may be searched at any time. - We are serious about this, folks.
Start time - 5PM - SHARP (Be there early - Once we get started the door is shut.)
Those taking the tour must be US citizens or Green Card holders carrying their green card.
- Closed toe shoes and long pants - Bring Safety Glasses if you have them. - Absolutely NO PHOTOGRAPHS. - CELL PHONES (MINIMUM) - Cell phones will
be turned OFF – we will not see them out of your pockets. If I hear a cell phone, the owner will hand it to me for the duration of the tour.
- This protocol can be heightened by security at any time.
We will sign in, and there will be a quick
security/safety orientation.
THURSDAY October 4, 2012SCV Reliability
MET Laboratories
EMC – Product Safety
US & Canada
• Electromagnetic Compatibility • Product Safety Cert. • Environmental Simulation • Full TCB Services • Design Consultations • MIL-STD testing • NEBS (Verizon ITL & FOC) • Telecom • Wireless, RFID (DASH7 & EPCglobal Test Lab)
Facilities in Union City and Santa Clara
www.metlabs.com [email protected] 510-489-6300
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 16
Robotics for Human Exploration of Space
Speaker: Dr. Terry Fong, Director, Intelligent Robotics
Group, NASA Ames Research Center Time: Presentation at 7:00 PM Cost: none Place: Carnegie Mellon University Silicon Valley,
Room 118, Building 23, Moffett Field RSVP: not required Web: ewh.ieee.org/r6/scv/ras
Dr. Terry Fong is the Director of the Intelligent Robotics Group at the NASA Ames Research Center. From 2002 to 2004, he was the deputy leader of the Virtual Reality and Active Interfaces Group at the Swiss Federal Institute of Technology (EPFL). From 1997 to 2000, he was Vice President of Development for Fourth Planet, a developer of real-time visualization software. Dr. Fong has published more than a hundred papers in field robotics, human-robot interaction, and robot user interfaces. He received his B.S. and M.S. in Aeronautics and Astronautics from the Massachusetts Institute of Technology and his Ph.D. in Robotics from Carnegie Mellon University.
Future human missions to the Moon, Mars, and
other destinations offer many new opportunities for exploration. Astronaut time, however, will always be limited and some work will not be feasible for humans to do manually. To address this, robots can be used to complement human explorers, performing work autonomously and under remote supervision from Earth. A central challenge, therefore, is to understand how human and robot activities can be coordinated to maximize mission success and scientific return.
Robots can do a variety of work to increase the productivity of human explorers. Robots can perform tasks (survey, inspection, etc.) that are tedious, highly-repetitive or long-duration. Robots can perform tasks ahead of crew, such as advance scouting, that help prepare for future human activity. Robots can work in support of crew, assisting or performing tasks in parallel. Robots can also perform "follow-up" work, completing tasks designated or started by humans.
In this talk, I will present some of the ways in which the NASA Ames Intelligent Robotics Group (IRG) has been working to improve human exploration of space. A central focus of our research has been to develop and field test robots that work before, in support, and after humans. Our approach is inspired by lessons learned from the Mars Exploration Rovers, as well as human spaceflight programs, including Apollo, the Space Shuttle, and the International Space Station.
THURSDAY October 4, 2012
SCV Robotics and Automation
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 17
Life Cycles for Portfolio and Program Management
Speaker: John Patton, PMP, President, CEO,
Cadence Management Corporation Time: Food & Networking at 6:00 PM;
Presentation 7:00 PM Cost: $2 donation for food Place: Cadence Design Systems, Building 10
(auditorium), 2655 Seely Avenue, San Jose RSVP: from website Web: www.ieee-scv-tmc.org
John Patton, PMP, is President, CEO and founder, of Cadence Management Corporation and creator of the methodology for practical application of practices identified in the PMI standards. Director of the Cadence Global Solution Provider Program, consisting of native speakers providing Cadence branded training and consulting services in the local language with the local culture in various countries around the world. Mr. Patton has had experience in all aspects of Organizational Project Management (OPM), from its roots in strategic planning into portfolios, programs and projects, through implementation into ongoing operations. A world-class consultant for companies like United Space Alliance (Space Shuttle), Starbucks Coffee, eBay, Logitech, and Boston Scientific, implementing his methodology and facilitating rapid project start-up planning.
Life Cycles for Portfolio and Program Management
Taking on a new scale of computer project? Integrating new products or operations into your business? Get a better compass before you embark.
This presentation differentiates between the standards and methodology of project management, program management and portfolio management. The life cycle (stage/gate) approach is established as a best practice and a basis for any methodology. Attendees will take away the concepts and structures of gate deliverables and decisions.
The talk relates the processes of the most recent standards, which are the Portfolio Management Standard, and the Program Management Standard, both in their second edition, to project, program, and portfolio life cycles, showing how all interrelate and coexist in an organization.
THURSDAY October 4, 2012
SCV Technology Management, with Computer
• Patent application preparation, prosecution, IP Strategy • Enforcing, Licensing and Monetizing Patents • Broad Experience in many Electrical and Software arts • Our Experts: IEEE Fellow, SPIE Fellow, Technical and Legal Experts
Ph: 408-288-7588 www.StevensLawGroup.com
Email: [email protected]
1754 Technology Dr, #226 San Jose
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 18
Heterogeneous System Architecture (HSA): An Overview
Speaker: Dr. Benedict R. Gaster, AMD Time: Networking at 6:30 PM; Presentation at 7:00
PM Cost: none Place: Cadence, Bldg 10, 2655 Seely Ave, San
Jose RSVP: from website Web: sites.ieee.org/scv-cs
Dr. Benedict R. Gaster is a software architect working on programming models for next-generation heterogeneous processors, particularly examining high-level abstractions for parallel programming on the emerging class of processors that contain both CPUs and accelerators such as GPUs. He has contributed extensively to the OpenCL’s design and has represented AMD at the Khronos Group open standard consortium. He has a Ph.D. in computer science for his work on type systems for extensible records and variants.
Heterogeneous computing is main stream; it can
be found in almost all modern media devices and it can be found in the cluster of the supercomputing world too. However, to date each system is different and heterogeneous can mean different ISAs, different memory buses, different execution models and on and on. This variation makes it almost impossible to build a single portable application. It is not always clear who benefits from this model, but one thing is certain: it is not the developer!
The Heterogeneous System Architecture (HSA) is intended to address these issues directly at the definition of the platform. Originally proposed by AMD, HSA is an industry wide foundation that in June 2012 released an abstract machine specification, including an execution model and memory model capable of supporting a wide range of programming models and languages ranging from C++11 to Java and beyond.
In this talk I will introduce HSA, providing examples, details of design choices, and much more besides.
TUESDAY October 9, 2012
SCV Computer
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 19
Pad Cratering, Lead Free and Density Challenges Facing
Electronics Packaging
Speaker: Chris Hunrath, Integral Technology Time: Optional dinner at 6:00 PM; Presentation at
6:45 PM Cost: $20 for dinner ($10 for students,
unemployed); no cost for presentation Place: Biltmore Hotel, 2151 Laurelwood Rd, Santa
Clara RSVP: from website Web: www.cpmt.org/scv
Chris Hunrath is the Vice President of Technology for Integral Technology, a manufacturing corporation focusing on the research and development of new products for emerging technologies. In his 30-year career in the electronics industry, Hunrath has contributed to several breakthrough products including many in the new Zeta product line offered by Integral. He is a recognized expert on pad cratering and HDI.
High-density electronics continues to increase
demands on Printed Circuit board materials and constructions. Added to that, the use of lead-free solder at higher assembly temperatures can impart latent mechanical stresses and at the same time embrittle the PCB material. Furthermore, increasing field performance requirements (such as for mobile devices) increase the need for better mechanical reliability. Density, thermal and mechanical pressures have increased the incidence of "Pad Cratering," a fracture defect found most commonly on BGA assemblies and leads to opens.
New film-based materials and combinations of materials create opportunities for PCB manufacturers to meet these demands. They allow the manufacturer to impart certain properties in specific layers. Indeed, these "laminar composites" will not only enable denser structures, but make them very reliable.
WEDNESDAY October 10, 2012 SCV Components, Packaging and Manufacturing Technology
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 20
Panel on Mobile Backhaul: Small Cells are a Big Deal; and
Small Cells and the Critical Role of Microwave
Speakers: Michael Howard, Principal Analyst-Carrier
Networks, Infonetics Research; Paul Kennard, CTO, Aviat Networks
Time: Neworking and refreshments at 6:30 PM; Presentations at 7:00 PM
Cost: $5 donation for food Place: Texas Instruments Building E, 2900
Semiconductor Dr., Santa Clara RSVP: from website Web: www.ewh.ieee.org/r6/scv/comsoc
Michael Howard co-founded market research firm Infonetics Research in 1990, and today is recognized as one of the industry’s leading experts in emerging markets, service provider trends, and user buying patterns. Michael leverages 40 years of communications industry and market research experience in analysis, vendor market share, forecasts, and operator surveys on carrier Ethernet, Ethernet access devices (EADs), Ethernet and IP MPLS VPN services, carrier routers and switches, mobile backhaul, content delivery networks (CDN), software-defined networks (SDN), and small cells. In 2008, along with Nan Chen and others, he co-authored Carrier Ethernet: Extending Ethernet Beyond the LAN, which received 5 out of 5 stars on Amazon.com. Today Michael moderates webinars, chairs conference programs, and speaks at industry events around the world, including the Broadband World Forum in Europe and Asia, CTIA Wireless, Carrier Ethernet World Congress, NetEvents, Carrier Ethernet World APAC, Telecom India, and CDN World Summit. He is frequently quoted in trade and business press such as Business Week, CNN Money, The Daily Deal, Forbes, Fortune, Investor’s Business Daily, Light Reading, Network World, New York Times, and The Wall Street Journal.
Paul Kennard has been the Chief Technical
Officer of Aviat Networks since January 2007. The company’s principal business is in designing and building of microwave networks in North America and around the world. (continued, next page)
Small Cells are a Big Deal Small cells, or more specifically, low power base
stations, have been part of mobile operator non-residential 3G rollouts for at least 5 years. They are not a big deal to date, with most small cells silently deployed in-building for 3G coverage, totaling less than 250,000 cumulative to date. The big fuss is about the slowly beginning rollout of outdoor picocells for capacity for 3G and later LTE. Outdoor small cells will principally be deployed on lightpoles, traffic lights, and the sides of buildings in urban cores, and their operation will be coordinated with the nearby macrocells, putting prime stress on capacity, latency, and timing/synch for backhaul. Another wrinkle: many outdoor deployments will include carrier WiFi, which brings both simplification and complexities to the network design and operation. Operators will use Ethernet copper and fiber where available, but will predominantly use microwave, millimeter wave, and NLOS microwave for the immediate small cell backhaul link. Clock timing/synch must be supplied to the small cells and IEEE 1588v2 is the preferred technology. North America has strikingly different macrocell backhaul trends versus the rest of the world, but small cell backhaul will face the same issues across the globe. The speaker and Infonetics team have conducted research for the past 2 years with mobile operators around the world, and will present their preferred architectures, backhaul technologies, design assumptions, vendors, and the daunting barriers. Outdoor small cell deployments are not going to be easy or quick, but they will be a big deal in the long run.
Small Cells and the Critical Role of Microwave
(continued, next page)
WEDNESDAY October 10, 2012
SCV Communications
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 21
(Paul Kennard, continued)
Backhaul of mobile networks is a good proportion of the Aviat business and they are one of the leaders in the network build out of LTE. Small cell backhaul represents a very interesting challenge in the backhaul arena and is a keen area of focus for the company.
Paul started with Digital Microwave Corporation in 1996 as VP of Engineering. As the company evolved and changed its name to Stratex, Harris Stratex and finally Aviat, Paul has held various job functions in addition to engineering. These included VP of Corporate Marketing & Product Development and VP of International Sales. He has experience of mobile networks all around the world.
Paul has been in the Bay Area practicing engineering since 1989 and prior to that was in Ottawa where he worked for BNR from 1980 to 1989. He started his career at Marconi in the UK in 1973 and also had a stint with Texas Instruments. He holds BS and MS degrees from UMIST in the UK. The majority of Paul’s experience has been directed towards innovation and development of wireless networks.
(Continued, from prev. page) Small Cells and the Critical Role of Microwave
Backhaul has become one of the most critical aspects of mobile networks. This is especially true in the implementation of LTE networks. The first part of this talk will focus on the experiences of building LTE backhaul solutions. The current backhaul solutions used for Macro Cells will clearly have to be different for Small Cells and the second part of the talk will address the challenges and the potential solutions. Finally, the future of Microwave Networking will be addressed and how the demands of the network evolution will influence innovation and what techniques and technologies will emerge to address the challenges.
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 22
Mini-Symposium: ESD Troubleshooting Techniques
for Electronic Designs; Fundamentals of Signal and
Power Integrity
Speakers: Doug Smith, D. C. Smith Consultants, and Prof. Ege Engin, San Diego State University
Time: Registration/breakfast at 7:30 AM; instruction from 8:30 AM - 5:00 PM; reception following
Cost: $250 for IEEE Members; $275 non-Members; $100 Students/Unemployed (includes lunch)
Place: Biltmore Hotel, 2151 Laurelwood Rd, Santa Clara
RSVP: from website Web: ewh.ieee.org/r6/scv/emc
Doug Smith held an FCC First Class Radiotelephone license by age 16 and a General Class amateur radio license at age 12. He received a B.E.E.E. degree from Vanderbilt University in 1969 and an M.S.E.E. degree from the California Institute of Technology in 1970. In 1970, he joined AT&T Bell Laboratories as a Member of Technical Staff. He retired in 1996 as a Distinguished Member of Technical Staff. From February 1996 to April 2000 he was Manager of EMC Development and Test at Auspex Systems in Santa Clara. He currently is an independent consultant specializing in high frequency measurements, circuit/system design and verification, switching power supply noise and specifications, EMC, and immunity to transient noise. He is a Senior Member of the IEEE and a former member of the IEEE EMC Society Board.
Dr. Ege Engin received his Ph.D from the University of Hannover, Germany. From 2005 to 2008, Dr. Engin was with the Packaging Research Center at Georgia Tech, where he was an Assistant Director of Research. Previously, he was with the Fraunhofer-Institute for Reliability and Microintegration (IZM), Berlin. Since 2008, he is an Assistant Professor in the Electrical and Computer Engineering Department of San Diego State University. He has more than 80 publications in journals and conferences in the areas of signal and power integrity modeling and simulation and three patents. He is the co-author of the book "Power Integrity Modeling and Design for Semiconductors and Systems," published by Prentice Hall in 2007. Dr. Engin is the recipient of the Semiconductor Research Corporation Inventor Recognition Award in 2009.
ESD Troubleshooting Techniques for Electronic Designs
Tracking down the sources of ESD problems in equipment can be difficult in modern electronic designs. After a brief overview of the characteristics of ESD and its effects on equipment, simple and effective troubleshooting techniques will be discussed that Mr. Smith has developed over many years of solving ESD problems. Live demonstrations will be used to illustrate some of the techniques.
Fundamentals of Signal and Power Integrity
As the clock frequencies for off-chip signals approach 20 GHz and beyond, maintaining signal and power integrity are becoming major issues to design a computer system that can actually support such speed. This mini-symposium will cover fundamentals of modeling, simulation, and characterization techniques to ensure signal and power integrity. The following topics will be covered in this tutorial:
Session 1: Power integrity modeling and design Session 2: Signal integrity modeling of losses Session 3: Advanced topics: Modeling of through
silicon vias for 3D ICs; power plane filtering using electromagnetic bandgap structures.
Reception & Exhibits: 5:00 PM - 6:00 PM
There will be an exhibition by vendors of EMC design, test and measurement products and services. During the reception in the exhibit area, heavy appetizers and beverages will be available. You are welcome to attend the reception only at NO CHARGE, provided a registration form is submitted in advance. Thus, if you can't join us for the entire day, drop by for the reception and exhibition to network with the speakers and attendees as well as vendors. You might even win a raffle prize! Anyone who ONLY wishes to attend the Reception & Exhibits must register. The Reception & Exhibits session is also organized as a PACE (Professional Activities Committees for Engineers) event under IEEE-USA.
THURSDAY October 11, 2012
SCV Electromagnetic Compatibility
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Motivating Our Students to Become Engineers:
How You Can Make It Happen
Speakers: Dr. Peter Staecker, 2012 IEEE President-Elect, and others
Time: Registration at 8:30 AM; seminar from 9:00 AM - 1:00 PM
Cost: none Place: Santa Clara County Education Office, San
Jose Room (Ground Floor, North Bldg.), 1290 Ridder Park Dr, San Jose
RSVP: required, from website Web: www.ieee4life.org
PROGRAM FEATURES: Opening remarks by Dr. Peter Staecker, 2012
IEEE President-elect. An eye-opening presentation by the former
Superintendent of a South Bay School district to discuss the problems of California public schools.
Speakers representing the following groups will tell us how volunteers can help students to regain America’s technical leadership:
• TOPS (Teaching Opportunities for Partners in Science)
• RE-SEED (Retiree Enhancing Science Education through Experiments and Demonstrations)
• IEEE TISP (Teacher In-Service Program) by Michael Lightner, IEEE VP of Educational Activities
Concurrently, in the same building a K-8 teacher conference will explore ways to incorporate technology into their teaching. Some of those teachers will also speak to us about their goals and needs. You’ll have opportunities to talk with the teachers and the IEEE officers during lunch.
California, next to last? In the United States, California K-8 students in
math and science rank – 49th! US students rank 19th and 24th among the
industrialized countries of the world! • Research shows those who don’t learn basic math
in early grades will struggle with algebra. • Kids whose interest isn’t sparked in science won’t
consider a career in engineering. • Kids weak in basic math and science who DO
enter engineering schools drop out. Who will develop the devices, circuits, systems,
high-speed trains and low-emission cars of the future? Who will find practical energy sources, solve the environmental problems and construct protection against global terrorism? If the present trend of poorly prepared American students continues, who will bring back America’s technical leadership?
Without an adequately educated population, America’s top schools can’t provide enough engineers for the US to solve the technical challenges of the 21st Century. China and India are graduating far more engineers than the US. If the trend continues, American companies will be forced to outsource even their design work.
The Santa Clara Valley and Oakland/East Bay IEEE Life Member Groups are offering an opportunity to explore ways to assist K-8 teachers’ effectiveness. Who better to inspire K-8 students in technical careers than our experienced engineers? By showing youngsters that engineering can be an exciting and important profession, practicing engineers can assist teachers in the classrooms to generate enthusiasm for the basic skills.
SATURDAY October 13, 2012
SCV and OEB Life Members
Patent Agent Jay Chesavage, PE
MSEE Stanford 3833 Middlefield Road, Palo Alto 94303
www.File-EE-Patents.com
TEL: 650-619-5270 FAX: 650-494-3835
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Novel Thermal Interface Materials for 3D Chip Stacks
Speaker: Srilakshmi Lingamneni, Ph.D Candidate,
Stanford Nanoheat Laboratory, Stanford University
Time: 12:00 PM Noon Cost: IEEE Members: $5; Non-IEEE Members:
$10 (Light lunch of pizza and drinks provided)
Place: TI Auditorium E-1, 2900 Semiconductor Drive, Santa Clara
RSVP: not required Web: www.ieee.org/nano
Srilakshmi Lingamneni received her B.Tech in Mechanical Engineering from Indian Institute of Technology, Madras in 2008 and M.S. in Mechanical Engineering from Stanford University in 2010. She is currently pursuing her Ph.D. in Mechanical Engineering at Stanford University. She was a Stanford Mechanical Engineering department teaching assistant for the academic years 2008-2010. Her research interests include development of various thermal interface materials for thermal management in electronics, with a particular focus on materials for 3D integrated chips.
This talk will present an overview of the broad
spectrum of research work being carried out at the Stanford Nanoheat Laboratory, the state of the art thermal characterization tools at our lab and the novel mechanical characterization tools that are being developed. It will discuss in detail the past work, latest developments and future directions of research in nanostructured interface materials. The talk will then explore the thermal challenges of 3D IC integration and new material requirements for thermal management in 3D packaging and discuss the novel interface materials that are being developed.
TUESDAY October 16, 2012
SCV Nanotechnology
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Wearable Robots for Today and Tomorrow
Speaker: Russ Angold, Co-Founder and CTO, Ekso
Bionics Time: Optional dinner, 6:15 PM, Stanford Hospital
Cafeteria. Meeting at 7:30 PM Cost: none (for meeting) Place: Room M-114, Stanford University Medical
School, Stanford RSVP: not required Web: www.ewh.ieee.org/r6/scv/embs
As CTO of Ekso Bionics, Russ Angold focuses on pushing the limits of technology to strategically advance the field of Bionic Exoskeletons across all market segments. Russ also works closely with the Lockheed Martin Corporation, licensing Ekso's technology to further develop the HULC exoskeleton for military use. Formerly Vice President of Engineering, Russ provided many of the concepts that shape today's current designs as well as those of the ExoHiker, ExoClimber and HULC. Before Ekso Bionics, Russ held various engineering positions at Rain Bird Corporation, Berkeley Process Control and the Irrigation Training, and Research Center in San Luis Obispo. Russ has a bachelor's degree in BioResource and Agricultural Engineering from California Polytechnic State University, San Luis Obispo. He is a California registered Professional Mechanical Engineer and holds five patents with another seven pending.
Ekso™ is a wearable robot or exoskeleton that enables people with lower-extremity paralysis or weakness to stand and walk. It is a ready to wear, battery powered, bionic device that is strapped over the user's clothing. Originally Berkeley Bionics, Ekso Bionics was founded in Berkeley , California in 2005. Ekso Bionics is committed to applying the latest technology and engineering to help people rethink current physical limitations and achieve the remarkable. Since inception Ekso Bionics has forged partnerships with world-class institutions like UC Berkeley, received research grants from the Department of Defense and licensed technology to the Lockheed Martin Corporation. Today Ekso Bionics continues to pioneer the field of exoskeletons, designing and creating some of the most forward-thinking and innovative solutions for people looking to augment human mobility and capability.
WEDNESDAY October 17, 2012
SCV Engineering in Medicine and Biology
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FPGA-Enabled Power Electronics Systems, Past to Present
Speaker: James Bonanno, consultant Time: Networking & Pizza at 6:00 PM,
Presentation at 6:30 PM Cost: Donations for food accepted Place: Texas Instruments, Building E Auditorium,
2900 Semiconductor Drive, Santa Clara RSVP: not required Web: www.ewh.ieee.org/r6/scv/pels
James Bonanno has been a member of IEEE for 22 years, and belongs to the Power Electronics (PELS), Industrial Electronics (IES), and Industry Applications (IAS) societies. He serves on the System on a Chip committee for the IES. He has been working with FPGA’s for power electronics since he designed a FPGA based digital controller in 1999 for an industrial UPS application. During his time in industry, he has consulted for various industrial and aerospace such as GE Aviation, Eaton, Lord, and Moog, and several entrepreneurial ventures. Specific interests are multi-axis and high performance AC drives and power electronic converter designs featuring FPGA based controls, hardware design and packaging, and system on system software design tools.
The ubiquitous DSP microcontroller is a long
standing aspect of digital control for power electronics and drive systems. During the last ten years, the emergence of the FPGA as a central feature in digital controls for power electronics has emerged, and in many cases is becoming the main component in digital control architecture. The advantages of deterministic loop timing, parallel processing, flexible design tools, and relatively low cost for high density devices are real. These features make the use of FPGA technology quite attractive for many applications. Particularly as the number of topologies in the application of power electronics proliferates, FPGA’s are well suited to the performance demands. Such applications may include multi-level converters, power factor correction, and alternative energy. This talk will feature some historical perspectives on FPGA use in power electronics, with specific industrial examples, and then migrate into present state of the art. Current applications are highlighted, then some time will be spent talking about the tools and techniques for FPGA based controllers. This includes the use of higher level languages for systematic generation of HDL firmware. The talk concludes with perspectives on the future of FPGA based power electronic systems.
WEDNESDAY October 17, 2012
SCV Power Electronics
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Accelerating Analog Design
Speaker: S. S. Mohan, Synopsys Time: Networking with pizza at 6:00 PM;
Presentation at 6:30 PM Cost: none Place: TI Auditorium E, 2900 Semiconductor Drive,
Santa Clara RSVP: from website Web: sites.ieee.org/scv-sscs
S. S. Mohan received the B.S., M.S. and Ph.D. degrees in Electrical Engineering from Stanford University, where he focused on the design and optimization of CMOS analog and RF circuits. He has twenty years experience in circuit design and automation and has designed GPS chips, medical electronics, Serdes RF LCOs and multi-phase VCOs, gigabit-ethernet front-ends and shunt-peaked amplifiers. He served as Chief Scientist at Sabio Labs prior to its acquisition by Magma Design Automation where he became Senior Director in charge of the analog and mixed-signal circuit design group. He has taught analog design classes at Stanford as a teaching assistant and visiting faculty and received the Centennial Award for Teaching. Mohan currently leads the circuit team at Synopsys that creates reusable PLL, ADC, Serdes, RF LCO, Bandgap, Opamp and regulator FlexCells leveraging its proprietary optimizer (ADX).
We investigate state-of-the art technology that
accelerates analog design by automatically custom sizing an architecture to satisfy specifications for a chosen process over process, voltage and temperature (PVT) variations. The talk begins with an overview of manual and automated circuit design methods and identifies the iterative and time-intensive steps that result in the analog bottleneck. We then describe how an equation-based optimizer and optimization friendly process-models are combined with a unified system and circuit formulation that is independent of specification and process to enable analog/RF circuits to be designed and ported efficiently while also documenting the operation of the circuit. Then, innovations and ease-of-use features that address difficulties associated with traditional equation based optimization methods are presented. The talk concludes with illustrative applications of commercial equation-based optimization tools in ADC, PLL, RF LCO, opamp, regulator and Serdes designs to highlight how this compelling methodology is leveraged for process and corner aware, simultaneous optimization of system and circuit across different levels of hierarchy and abstraction.
THURSDAY October 18, 2012
SCV Solid State Circuits
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Addressing the Grid Integration Challenges of High-Penetration
Photovoltaic Systems Speaker: Robert Johnson, SunPower Time: Networking at 5:30 PM; Presentation at
6:15 PM; Dinner at 7:15 PM; Presentation continues after dinner
Cost: $25 for IEEE members; $30 for non-members; $15 for student and retired members
Place: Zio Fraedos, 611 Gregory Lane, Pleasant Hill
RSVP: by email by October 15 to Michael Nakamura, [email protected] or call 510-287-2066
Web: www.e-grid.net/docs/1210-eob-ias.pdf
Robert Johnson manages the SCADA Group at SunPower and is responsible for the overall execution of monitoring and controls solutions for Utility Scale and large Commercial photovoltaic projects. He works closely with R&D, O&M, Sales, EPC and other groups to ensure SunPower delivers industry leading SCADA products and services. Robert has led the design and implementation of SCADA systems for 600MW+ of Utility PV Plants and has extensive PV system design experience working with clients that include FPL, Wal-Mart, Dow Chemical Company, Applied Materials, the Department of Energy, Macy's, Castle & Cooke, Xcel Energy, NRG Energy, Iberdrola, and others. Robert has presented at various IEEE and industry conferences on the topics of renewables and grid integration.
The rapidly growing penetration of photovoltaic
power systems poses new technical and policy challenges as we work to integrate these distributed and variable generation resources into our electrical grids. This presentation will look in detail at various supervisory control and data acquisition (SCADA) systems and applications used to address these challenges. These include automatic voltage regulation, curtailment control, synchrophasors, and others. It will also examine the interconnection requirements and system performance characteristics driving these applications.
This presentation will look at aspects of Utility-Scale PV system configurations and design, modeling and validation, system dynamics, communication and control infrastructure, and other related topics.
THURSDAY October 18, 2012
OEB Industry Applications
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Antenna Synthesis: A New Way to Approach Antenna Design
Speaker: Dr. Jason Lohn, Associate Professor, Carnegie Mellon University Silicon Valley
Time: Networking with food at 6:30 PM; Presentation at 7:00 PM
Cost: none Place: Carnegie Mellon University, Building 23,
Moffett Field RSVP: from website Web: sites.ieee.org/scv-aps
Dr. Jason Lohn is an Associate Research Professor in Electrical and Computer Engineering at Carnegie Mellon University. He led a team of scientists and engineers to successfully evolve, develop and fly three evolved X-band antennas in space aboard NASA’s Space Technology 5 mission in 2006. His main interests are to research and develop search algorithms that can automatically design and optimize hardware systems to achieve increased performance and reliability in application areas such as antenna design, microelectro-mechanical systems, robotics, and spacecraft design.
Current methods of designing and optimizing antennas by hand are time and labor intensive, limit complexity, and require significant expertise and experience. AI search algorithms can overcome these limitations by automatically searching the design space and finding effective solutions that are closer to limits imposed by physics. For example, our algorithms have discovered counter-intuitive antenna designs that out-perform traditionally designed systems. While optimization modules are commonly available in commercial RF CAD tools, they are typically simple parametric methods, and no system yet offers an antenna synthesis capability. We discuss the antenna synthesis system we are developing and its use in a variety of applications, including a project that produced antennas that flew in space on NASA’s Space Technology 5 (ST5) mission.
THURSDAY October 18, 2012SCV Antennas and Propagation
Channel Partner
Multiphysics, Multidisciplinary Engng CFD, Stress, Heat Transfer, Fracture Fatigue, Creep, Electromagnetics Linear/Nonlinear Finite Element Analyses Multi-objective Design Optimization BGA Reliability
Ozen Engineering (408) 732-4665
[email protected] www.ozeninc.com
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Smart Grid: Opportunities for Innovation
Panelists: Andy White, CEO, Trilliant; Brian
Thompson, CEO, Stem; Lisa Caswell, President, eMeter; Steve Malnight, VP, Pacific Gas & Electric
Time: Dinner and Networking and 6:00 PM; Presentations at 7:00 PM
Cost: $35 IEEE members, $45 non members Place: Orrick, Herrington & Sutcliffe LLP, 1000
Marsh Road, Menlo Park RSVP: from website Web: www.ewh.ieee.org/r6/scv/pes_ias
Neill Armstrong once said that our electric grid was
one of the greatest engineering achievements of the 20th century. Yet, in the next few decades, our electric grid will need to be modernized to meet the evolving energy challenges of the 21st century. These include increasing renewable energy generation and dealing with the proliferation of distributed energy resources such as rooftop solar panels, electric vehicles, energy storage, and smart appliances, while keeping electric energy supply inexpensive and reliable.
But with challenges come opportunities for innovation. New technologies such as grid data networking, smart meters, analytics and demand response algorithms will help modernize our electric grid and benefit consumers and utilities alike through enhanced energy efficiency, improved reliability, the ability to integrate new sources of energy generation, including at the local level.
What new technologies, solutions, and business model innovations are required to allow a Smart Grid to be able to realize its potential to deliver these benefits, including adapting to emerging distributed energy resources?
Smart Meters, aka advanced metering infrastructure (AMI), have been deployed throughout the state, but Time-of-Use (TOU) rates or dynamic pricing have not yet been implemented. Will they be mandated so consumers can start managing their energy bills better?
With the smart grid, more energy devices will be networked and a lot of Big Data will flow. What innovations are needed to be able to analyze the data and optimize supply and demand in order to deliver benefits to energy providers and consumers?
Please join us to learn about the numerous Smart Grid innovation opportunities from top executives of leading smart grid companies in the Bay Area!
THURSDAY October 25, 2012
SCV Power & Energy and Industry Applications
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Senior Member Advancement Mixer
Helpers: current IEEE Fellows and Senior Members Time: 6:00 PM to 8:00 PM for the "Senior Mixer";
6:00 PM to 10:00 PM for exhibits and general exhibit viewing
Cost: $10 for member, $5 each for accompanying family members (up to 3). No cost for current Fellows, Senior Members (for 1/2-hour help with advancement reviews)
Place: Chabot Space & Science Center, 10000 Skyline Blvd, Oakland
RSVP: from website; limited to 60 Web: www.ewh.ieee.org/r6/oeb
The Oakland East Bay Section is hosting an
Advancement Mixer to assist Members to upgrade to Senior Member and encourage grade advancement in our Section. We have a capacity of 60 planned so sign up early – details to follow for registering.
We encourage Members to bring their family or friends to enjoy the Chabot Space and Science Center. We will have the facility reserved just for our group with access to the Beyond Blast Off Exhibit.
For Senior Members and Fellows, there will be no charge, but we ask that you volunteer to assist the referral team for a half-hour or more.
Senior Member Candidates need to review the application process on the IEEE website at:
www.ieee.org/membership_services/membership/senior/senior_requirements.html
OEB will provide the qualified members who will provide applicant referrals for you. Please bring your hard copy resume’ for use by the referral team.
Questions? – Send to Rosanna at
THURSDAY October 25, 2012
OEB Section
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Applications of Extreme Value Theory to Signal Processing
Subject: Speaker: Dr. Adam Rowell, Stanford University Time: Presentation at 7:00 PM Cost: none Place: Packard 101, Stanford University, 350 Serra
Mall, Stanford RSVP: from website Web: ewh.ieee.org/r6/scv/cis
Adam Rowell is currently finishing his PhD in Electrical Engineering at Stanford University under Dr. Bernard Widrow. His research focus is using Extreme Value Theory to solve signal processing problems, including optimizing the performance of quantized digital filters, and estimating overflow rates of fixed-point digital systems. Past research has also involved studying adaptive signal processing algorithms, and working on classifying different types of epilepsy in children using EEG signals. He has previously worked for the Signal Processing Toolbox and Fixed-Point Toolbox teams at The MathWorks Corporation, where he worked on tools for converting digital systems from a floating-point design to a fixed-point implementation. After completing his PhD in the fall of 2012, he will begin working at Exponent Consulting, doing failure analysis and rapid prototyping in the Electrical Engineering and Computer Science division, with emphasis on signal processing applications.
Extreme value theory (EVT) is the study of the
statistics of the extreme outliers in a random process. It is especially useful for estimating probabilities of an extreme event when little or no past data has been recorded at a similar level. Canonical examples of its application include predicting annual maximum river or wave heights and estimating worst-case insurance or stock market losses. Many problems in electrical engineering can benefit from the application of EVT, though such research is just getting started. In this talk, we will go over the basics of extreme value theory and show how its principles are useful to a few signal processing applications.
Both examples we investigate will illustrate how existing problems in electrical engineering can be easily tackled using EVT, yielding useful models. For the first application, we investigate the effects of quantization on digital filter performance. When digital filter coefficients are quantized, as is common in high-speed or low-power hardware, the performance can be significantly degraded. We will start with a quick overview of simple digital filters and their frequency response, and will see the effects of quantization on performance. Extreme value theory will then be applied to the frequency response of the quantized filter to model how the quantization affects the maximum response error. In our second example, we will use extreme value theory to model overflow rates in digital systems. Even without knowing the underlying distributions of the data being analyzed, EVT can accurately estimate the rate at which a value will exceed a high threshold.
FRIDAY October 26, 2012
SCV Computational Intelligence, with Signal Processing, Circuits & Systems, Robotics & Automation
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Nanovation: From Science to Startups
(Seminar)
Speakers: Carol Mimura, UC-Berkeley; Mark Bunger,
LUX Research; Shadi A. Dayeh, UC-SD & Los Alamos National Lab; Jessica Koehne, NASA Ames Research Center; Zvi Or-Bach, MonolothICTM 3D & Zeno Semiconductor; Zachary Smith, UC-Davis Medical Center; Robert Walters, Integrated Plasmonics Corp; Ben Wang, Svaya Nanotechnologies; Eli Yablonovitch, UC-Berkeley
Time: 9:00 AM - 5:00 PM Cost: IEEE Members: $50; Non-members: $75;
students: free (includes light breakfast and lunch)
Place: Stanley Hall, UC Berkeley Campus, University Drive, Berkeley
RSVP: from website Web: www.ieee.org/nano
Nano Chapter, in association with E3S, NSF, & BNC Since its conceptualization by Dr. Richard
Feynman, Nanotechnology has come a long way in its development and the Nanotechnology Age is the likely successor of the Information Age. Its penetration in electronics, medicine, textiles etc. has been disruptive in many arenas of science and technology. Due to its enormous potential, Researchers, Entrepreneurs, and Investors have shown tremendous interest in Nanotechnology and invested significantly each in their own way. This symposium is focused on bringing together the unique perspectives of these three groups and reviewing the progress so far and the ever widening landscape of Nanotechnology. Centered on the current activities of students and recent graduates, this event will include a poster session and a business plan competition.
Confirmed Speaker List:
Keynote: Carol Mimura, Assistant Vice Chancellor for Intellectual Property & Industry Research Alliances UC, Berkeley
Mark Bunger, Director of Research, LUX Research Shadi A. Dayeh, Prof, Dept of ECE, UCSD. Fellow,
Center for Integrated Nanotechnologies at Los Alamos National Lab
Jessica Koehne, Nano-bio sensing systems Scientist at NASA Ames Research Center
Zvi Or-Bach, Founder & CEO of MonolothICTM 3D, Director of Zeno Semiconductor, serial entrepreneur
Zachary Smith, Project Scientist and Fellow, Center for Biophotonics Science and Technology, UC Davis Medical Center
Robert Walters, President and CEO Integrated Plasmonics Corporation
Ben Wang, Founder and Vice President of Svaya Nanotechnologies
Eli Yablonovitch, Prof, Dept of EECS UCB, Director NSF Center for Energy Efficient Electronics Science
SATURDAY October 27, 2012
SCV Nanotechnology
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Spin Caloritronics
Speaker: Pr. Gerrit E.W. Bauer, PhD, Institute of Materials Research, Tohoku University
Time: Networking and pizza at 7:00 PM; Prsentation at 7:30 PM
Cost: none Place: Western Digital, 1710 Automation Parkway,
San Jose RSVP: not required Web: ewh.ieee.org/r6/scv/mag
Pr. Gerrit E.W. Bauer, PhD holds an Engineering Degree (1980) in Chemical Technology from Twente University (The Netherlands) and Doctor Degree in Physics (1984) from the Technical University Berlin (Germany) for research carried out at the Hahn-Meitner-Institute of Nuclear Research. After a postdoc at the Institute for Solid State Physics at the University of Tokyo (1984-86), he became a member of the Scientific Staff of the Philips Research Laboratories (1986-92). He was appointed Professor of Physics at Delft University of Technology in 1992 and at Tohoku University in 2011. He (co)authored >200 refereed scientific papers in the area of condensed matter physics, in the last two decades mainly in the field of magnetoelectronics/spintronics. He received the Wilhelm-Conrad-Röntgen Award from Würzburg University (2000), the Outstanding Referee Award by the American Physical Society (2008), the Lars Onsager Medal from the Norwegian University of Science and Technology (2009). He became Fellow of the American Physical Society in 2010 “for exposing the interaction between spin transport, magnetization dynamics, charge and heat transport, and mechanical motion”.
The spin degree of freedom of the electron affects
not only charge, but also heat and thermoelectric transport, leading to new effects in small structures that are studied in the field of spin caloritronics (from calor, the Latin word for heat). This lecture addresses the basic physics of spin caloritronics. Starting with an introduction into thermoelectrics and Onsager’s reciprocity relations, the generalization to include the spin dependence in the presence of metallic ferromagnets will be addressed. Using this foundation I will describe several recently discovered spin-dependent effects in metallic nanostructures and tunneling junctions as well as a zoo of spin-related thermal Hall effects in terms of a two spin-current model of non-interacting electrons.
Next, I will argue that different classes of spin caloritronic effects exist that can be explained only by the collective spin dynamics in ferromagnets. The thermal spin transfer torque that allows excitation and switching of the magnetization in spin valves as well as the operation of nanoscale heat engines is complemented by thermal spin pumping. The latter generates the so-called spin Seebeck effect, which is generated by a heat current-induced non-equilibrium of magnons at a contact between an insulating or conducting ferromagnet and a normal metal. Under these conditions a net spin current is injected or extracted from the normal metal that can be detected by the inverse spin Hall effect.
Both classes can be formulated by scattering theory of transport in the adiabatic approximation for the magnetization dynamics and computed in terms of material-dependent electronic structures. Further issues to be addressed are the relation between electric, thermal and acoustic actuation, as well as the application potential of spin caloritronics.
MONDAY November 5, 2012
SCV Magnetics
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Crime.com - Post-Modern Criminal Behavior
Speaker: Dr. Hal Berghel, University of Nevada, Las
Vegas and CS Distinguished Lecturer Time: Networking/Refreshments at 6:30 PM;
Presentation at 7:00 PM Cost: none Place: Cadence, Bldg 10, 2655 Seely Ave, San
Jose RSVP: from website Web: sites.ieee.org/scv-cs
Dr. Hal Berghel is currently Professor of Computer Science at the University of Nevada, Las Vegas where he has previously served as Director of the School of Computer Science and Associate Dean of the College of Engineering. He is also the founding Director of the Identity Theft and Financial Fraud Research and Operations Center. His research interests are wide-ranging within the binary and digital ecosystem, ranging from logic programming and expert systems, relational database design, algorithms for non-resolution based inferencing, approximate string matching, digital watermarking and steganography, and digital security (including both computer and network forensics). Since the mid-1990′s he has applied his work in digital security to law enforcement, particularly with respect to digital crime, cyberterrorism, and information warfare. His research has been supported by both industry and government for over thirty years. His most recent work in secure credentialling technology was funded by the Department of Justice. In addition to his academic positions, Berghel is also a popular columnist, author, frequent, talk show guest, inventor, and keynote speaker. For nearly fifteen years he wrote the popular Digital Village column for the Communications of the ACM.
Berghel is a Fellow of both the Institute for Electrical and Electronics Engineers and the Association for Computing Machinery, and serves both societies as a Distinguished Visitor and Distinguished Lecturer, respectively. He has received the ACM Outstanding Lecturer of the Year Award four times and was recognized for Lifetime Achievement in 2004. He has received both the ACM Outstanding Contribution and Distinguished Service awards. He is also the founder and owner of Berghel.Net, a consultancy serving business and industry, and co-owner of BC Innovations Management, a startup company in IP and DRM.
This talk begins with an overview of the role of
crime in general, and digital crime in particular, in the shadow economies of the world. It illustrates this via a sequence of specific criminal activities that have been studied by the author. This talk will explain the latest digital crime scene in terms of sources, modus operandi, and the digital techniques involved. Examples will be drawn from actual case files and published media reports, and the techniques will be explained and in some cases actually demonstrated. Exploits include: bank card skimming, ATM hacking, digital gas pump hijacking, phishing scams, bank card brokering and internet dumpsites, hotel room invasions, physical counterfeiting (e.g., Superdollar), digital counterfeiting and some brute-force techniques as well. If your organization is interested in the latest digital exploits of the denizens of digital darkness, this talk is for you.
WEDNESDAY November 14, 2012
SCV Computer
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Cost Versus Reliability Tradeoffs for Stacked Devices
Speaker: Steve Steps, Senior Director of Wafer Level Burn-In & Test, Aehr Test Systems
Time: Optional dinner at 6:00 PM; Presentation at 6:45 PM
Cost: $20 for dinner ($10 for students, unemployed); no cost for presentation
Place: Biltmore Hotel, 2151 Laurelwood Rd, Santa Clara
RSVP: from website Web: www.cpmt.org/scv
Steve Steps has been the Senior Director of Wafer Level Burn-In and Test at Aehr Test Systems for the last 12 years. Prior to joining Aehr Test Systems, Steve worked at KLA and worked for 19 years at the Hewlett-Packard Company. Steve has had over 20 technical papers accepted at conferences around the world. Steve's educational background includes a BS degree in Electrical Engineering, a BS degree in Computer Science and a Masters Degree in Electrical Engineering.
The industry demand for high feature-sets in very small, light products such as digital cameras, smart phones, medical devices and automotive electronics has driven a variety of high density packaging techniques. To achieve this high density, a wide variety of 3D packaging methods have been developed. The latest technique for stacking die is the Through Silicon Via (TSV) technology under development in many companies.
Although stacking has been very effective in improving the density of the resulting device, it has been decreasing the overall reliability of the device. Many of the same markets that are driving for high density are also becoming more reliability sensitive. It was easy to throw away a simple cell phone if it failed. However, modern smart phones are both much more expensive and contain more content that the user does not want to lose. Reliability demands are even higher if the device is being used for medial or automotive purposes.
This presentation will examine the reliability implications of stacked die. It will cover why reliable die ("Known Good Die -- KGD") is becoming more critical, what are the conditions that affect both the reliability and the need for KGD, and close with a case study of a technique for producing KGD: Wafer-Level Burn-In (WLBI).
WEDNESDAY November 14, 2012 SCV Components, Packaging and Manufacturing Technology
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Fuel Cells, Hydrogen and the California Carbon Mandate
Speaker: Prof. Donald Anthrop, San Jose State
University (retired) Time: Networking and buffet dinner at 6:00 PM;
Presentation following Cost: $15 Place: Willow Tree Restaurant, 6513 Regional St,
Dublin RSVP: from website Web: www.ieee4life.org
Donald Anthrop received a B.S. in chemistry from Purdue University in 1957 and a Ph.D. in materials engineering from the University of California, Berkeley, in 1963. He specialized in high-temperature thermodynamics. He feels fortunate and honored to have studied thermodynamics from two renowned researchers, Professors Alan Searcy and William Giauque. Prof. Giauque was awarded the Nobel Prize in chemistry in 1949 for experimentally verifying the third law of thermodynamics.
After receiving his Ph.D., he worked in the aerospace industry, Avco Corporation, for several years and then at Lawrence Livermore Laboratory. In 1968, he accepted a teaching position at Dominguez Hills State College, which at the time was the newest campus in the State University system. In 1971, he joined the faculty at San Jose State University to work in a new program in environmental science. He was only the second faculty member in that program at the time. At SJSU, he taught primarily energy and water courses. He retired from SJSU in 2004, returning occasionally to teach a course. He has over 70 published papers. One of his first papers on energy, "The Environmental Side Effects of Energy Production," was published in the Bulletin of Atomic Scientists in 1970.
For the environmentalists convinced that global
warming caused by carbon dioxide emissions will destroy the planet, motor vehicles powered by fuel cells operating on hydrogen seemed like a sure way to reduce carbon dioxide emissions. Prodded by the big environmental organizations, and lacking any knowledge of thermodynamics, in 2004 former Governor Arnold Schwarzenegger unveiled his so-called California Hydrogen Highways plan that set a goal of 100 statewide fueling stations by 2010 and a longer tern goal of 250 stations. According to the US Department of Energy, there are currently 23 stations in the state.
The environmental lobby would like us to believe that the only impediment to their brave new world of hydrogen-powered vehicles is a lack of refueling stations. To the contrary, the real problem lies in the production of hydrogen.
The actual energy required to produce a kg of hydrogen by electrolysis of water is 56.3 kw-hrs. After subtracting the energy required to compress the gas for use in a motor vehicle, the energy obtained from the reaction of a kg of hydrogen in a fuel cell is only 17.4 kw-hrs. There are about 19.8 million automobiles and 14 million light trucks, vans, and sport utility vehicles registered in California. If all of the automobiles were small cars like the Chevy Volt, about 260 billion kw-hrs of electrical energy would be required to produce and compress the hydrogen needed to power this fleet of fuel cell vehicles. This electrical energy is equivalent to about one-third of the total annual nuclear generation in the U.S. To produce this hydrogen would require construction of about 35,000 Mw of new nuclear generation, which is equivalent to 17 new Diablo Canyon plants.
Replacing the entire fleet of 19.8 million cars with fuel cell vehicles would reduce carbon dioxide emissions by 73 million tons – just 0.2 percent of the world total – provided no fossil fuels were used to produce the hydrogen.
WEDNESDAY November 14, 2012
OEB Life Members
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 38
Transformer Failure Due to Circuit Breaker Induced
Switching Transients Speakers: Dave Shipp and Thomas Dionise, Eaton
Corp Time: No-host social at 5:30 PM; Presentation at
6:15 PM; Dinner at 7:15 PM; Presentation continues at 8:00 PM
Cost: $25 for IEEE members, $30 for non-members, $15 for student and retired members
Place: Zio Fraedos, 611 Gregory Lane, Pleasant Hill
RSVP: by November 12 to Michael Nakamura, [email protected] or telephone (510) 287-2066
Web: www.e-grid.net/docs/1211-oeb-ias.pdf
David D. Shipp, PE, (S’72-M’72-SM’92-F’02) received the B.S.E.E. degree from The Oregon State University in 1972. He is a Principal Engineer for Eaton Corporation’s Electrical Services and Systems Division and a Fellow of the IEEE. He is a distinguished scholar in power system analysis and has worked in a wide variety of industries. He has spent many years performing the engineering work associated with his present-day responsibilities, which include a wide range of services covering consulting, design, power quality, arc flash, and power systems analysis topics. Over the last few years, he has pioneered the design and application of arc-flash solutions, modifying power systems to greatly reduce incident energy exposure. Present day topics cover switching transient induced failures of transformers. He has written over 85 technical papers on power system analysis topics. More than 12 technical papers have been published in IEEE/IAS national magazines and two in EC&M . He spent ten years as a professional instructor, teaching full time. He occasionally serves as a legal expert witness with a specialty in forensics (failure analysis). Mr. Shipp is currently the Chair for the IEEE I&CPS-sponsored Working Group on generator grounding. He has received an Industry Applications Society (IAS)/IEEE Prize Paper Award for one of his papers and conference prize paper awards for six others. He received the 2011 IEEE Richard H. Kaufmann award. He is very active in IEEE at the national level and helps write the IEEE Color Book series standards.
(Continued, next column)
Switching transients associated with circuit
breakers have been observed for many years. Recently this phenomenon has been attributed to a significant number of transformer failures involving primary circuit breaker switching. These transformer failures had common contributing factors such as 1) primary vacuum or SF-6 breaker, 2) short cable or bus connection to transformer, and 3) application involving dry-type or cast coil transformers and some liquid filled. This paper will review these recent transformer failures due to primary circuit breaker switching transients to show the severity of damage caused by the voltage surge and discuss the common contributing factors. Next, switching transient simulations in the electromagnetic transients program (EMTP) will give case studies which illustrate how breaker characteristics of current chopping and re-strike combine with critical circuit characteristics to cause transformer failure. Design and installation considerations will be addressed, especially the challenges of retrofitting a snubber to an existing facility with limited space. Finally, several techniques and equipment that have proven to successfully mitigate the breaker switching transients will be presented including surge arresters, surge capacitors, snubbers and these in combination.
Thomas J. Dionise, PE, (S ’79-M ’82-SM ’87)
received the B.S.E.E. degree from The Pennsylvania State University in 1978, and the M.S.E.E. degree with the Power Option from Carnegie Mellon University in 1984. He is currently a Power Quality Engineering Specialist in the Power System Engineering Department, with Eaton Corporation, Warrendale. He has over 27 years of power system experience involving analytical studies and power quality investigations of industrial and commercial power systems. In the metals industry, he has specialized in power quality investigations, harmonic analysis and harmonic filter design for electric arc furnaces, rectifiers and VFD applications. He co-authored a paper which received the 2006 Metal Industry Committee Prize Paper Award. Mr. Dionise is the Chair of the Metal Industry Committee and member of the Generator Grounding Working Group. Tom has served in local IEEE positions and had an active role in the committee that planned the IAS 2002 Annual Meeting in Pittsburgh. He is a licensed Professional Engineer in Pennsylvania.
THURSDAY November 15, 2012
SCV Industry Applications
October 2012 V is i t us a t w w w . e - G R I D . n e t Page 39
One-Day Conference: Solutions to the
Software Patent Problem
Speakers: over 25 speakers, moderators, and panelists
Time: 8:30 AM to 5:30 PM (includes lunch) Cost: $40 for IEEE members, $60 for in-house
counsel, $125 for non-members Place: Locatelli Activity Center, Santa Clara
University, 500 El Camino Real, Santa Clara RSVP: from website Web: www.CaliforniaConsultants.org John Allison, School of Business, UT- Austin Keith Bergelt, Open Innovation Network James Bessen, Boston University School of Law Brad Burnham, Union Square Ventures Colleen Chien, Santa Clara University School of Law Andrew Chin, University of North Carolina John Duffy, Univ of Virginia School of Law Nair Flores, Facebook Hon. Paul Grewal, Northern District of California Andrew Hirschfeld, US Patent and Trademark Office Heidi Keefe, Cooley LLP Amy Landers, McGeorge College of Law Ben Lee, Twitter Mark Lemley, Stanford Law School Brian Love, Santa Clara University School of Law Peter Menell, UC Berkeley School of Law Jason Mendelson, Foundry Group Michael Meurer, Boston University School of Law Suzanne Michel, Google Inc. Christina Mulligan, Yale Law School Kristen Osenga, Univ of Richmond School of Law Arti Rai, Duke Law School Hon. Edith Ramirez, Federal Trade Commission Dan Ravicher, Public Patent Foundation Michael Risch, Villanova Law School Julie Samuels, Electronic Frontier Foundation Pam Samuelson, UC Berkeley School of Law Wendy Seltzer, Yale Law School Christal Sheppard, Univ of Nebraska College of Law Ted Sichelman, Univ of San Diego School of Law Richard Stallman, Free Software Foundation Jennifer Urban, UC Berkeley School of Law Samson Vermont, University of Miami School of Law Kent Walker, Google
Normally an academic-oriented conference would
debate the merits of software patents. This conference is different. Rather than having another debate, this conference will use a premise -- that software patents are a problem -- as a springboard for discussing ways to address those problems. In rapid succession, patent experts at the conference will present innovative proposals (ranging from abolishing software patents to company/industry self-help), debate their relative merits, and discuss how they might be implemented. To extend the discussion, many of the speakers and other interested experts will publish short essays in Wired.com describing their proposed solution and advocating for its adoption. We hope conference attendees and Wired.com readers will embrace the best proposals and catalyze real action towards solving the software patent problem.
Organizers: Santa Clara Law Professors Colleen Chien and Eric Goldman.
FRIDAY November 16, 2012
SCV Consultants' Network of Silicon Valley