low power cmos vga

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370 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 42, NO. 6, JUNE 1995

A Low-Power CMOS VGA for 50 Mb/sDisk Drive Read ChannelsRamesh Harjani, Member, IEEE

Abstract- We describe an all CMOS variable gain amplifier(VGA) suitable for use in disk drive read channels. The VGAmaintains a 3 dB bandwidth greater than 85 MH z throughout itsgain range. This ensures good phase linearity for data transferrates of up to 50 Mbls. The VGA provides a 25 dB gain variationalong an ideal exponential gain to control voltage curve and30dBof gain control if ideal exponential characteristics s not absolutelynecessary. The VGA achieves the necessary exponential gainto control voltage characteristics intrinsically using only MOStransistors as a single unit to reduce power and area consumption.Overall power consumption is less than 10 mW for the VGAcircuit excluding the off-chip buffer circuits.

I. INTRODUCTIONHE desire for smaller disk drives with reduced powerT onsumption increases the need to integrate the readchannel electronics into a single mixed-signal CMOS chip

or a set of chips. Variable gain amplifiers (VGA) form animportant component of the read channel and help stabilize thevoltage supplied to the detector and filter sections of the readchannel. Standard bipoiar VGAs [ l ] dissipate lots of powerand previous attempts at developing a CMOS compatible VGA[2]have resulted in variable gain amplifiers with the necessarygain control characteristics but still dissipating substantialpower. A significant percentage of this power is dissipated ingenerating the exponential current output for a linear voltageinput. The exponential gain to linear control voltage character-istic is preferred for read channel automatic gain control loops[1]-[4] to minimize variations in the output voltage. Here wepresent a methodology for generating the desired exponentialtransfer characteristics intrinsically using only MO S deviceswithin the variable gain amplifier structure. It is usually notpossible to operate the MOSFET in the weak inversion regionbecause of the high frequencies involved in the signal path ofread channels. Therefore, for these frequencies in CMOS thereis no intrinsic logarithmic device transfer characteristics thatcan be exploited to generate the necessary exponential gainto linear control voltage characteristic desired. One possiblemethodology to generate this exponential characteristic is touse the parasitic lateral bipolar transistors available in CMOS121, 151, 161. An alternate methodology, being presented here,is to use the exponential gain control behavior presented bythe function

Manuscript received October 6, 1993; revised November 30, 1994. ThisThe author is with the Department of Electrical Engineering, University ofIEEE Log Number 9411334.

paper was recommended by Associate Editor M. Steyaert.Minnesota, Minneapolis, MN 55455 USA.

J-1.0 -0.6 -0.2 x 0.2 0.6 1O

Fig. 1. Exponential gain versus control voltage.

Gain = {H}(1 + x ) 2(1- x)2Gain range =-

This expression is plotted in Fig. 1, where the y scale isin dBs. It is possible to see that the gain expression in (1)provides the necessary exponential transfer Characteristics andshows a good match for -0.7 < x < 0.7. Further, it can beshown that the maximum gain range is given by (2). Therefore,for a gain range of 30 dB the value of x needs to be variedfrom -0.698 to +0.698. As just mentioned, the exponentialcharacteristics matches fairly well within this range. Outsidethis region ( - 0 . 7 ~ ~.7) the rate of change in gain is evenmore rapid. As it turns out this provides even better control ofthe output voltage in comparison to a simple exponential gaincharacteristics. A comparison of the output voltage producedusing the normal exponential scheme and our scheme is shownin Fig. 3. The system level block diagram, shown in Fig. 2,for the automatic gain control loop was used to obtain thevoltages in Fig. 3. The value of error voltage amplification, K ,was set to 1. A higher value of K would lead to better outputcontrol for both schemes. However, for comparison purposesany value is appropriate. For the two schemes only the transferfunction block between E , and A was changed. We note inFig. 3that at both higher and lower input voltages our schemeperforms better than an ideal exponential in maintaining aconstant output voltage. Therefore, the value of z could bevaried beyond f0 .7 . However, varying z beyond these limitshas detrimental affects on bandwidth and phase characteristicsand is discussed later.

1057-7130/95$04.00 0 1995 IEEE


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HARJANI: LOW-POWER CMOS VG A 37 1

A I

Fig. 2. Automatic gain control circuit used to compare VGA's.

Fig. 3. Output voltage produced using exponential and [ (l-x )/( +x)]schemes.11. CIRCUIT ESIGN

For a CMOS process the (( 1+ z ) / ( l - z)} function,displayed in Fig. 1, can be generated by dynamically varyingthe saturation region transconductance or the triode regionresistance of a transistor [7], [8]. The triode region resistancecan be changed by altering the gate voltage of a MOS devicewhile the saturation region transconductance can be controlledby altering the drain-to-source current through the device.We have selected to use the current control technique, i.e.,we alter the transconductances of transistors to generate thedesired function. Unfortunately, the transconductance of theMOS device varies only as the square root of the drain currentsuch that a single gain stage would only provide 15dB of gainvariation for z changing from -0.7 to +0.7. By varying thecurrent through a transistor we are altering its transconduc-tance. Unfortunately, a change in the transconductance alsoaffects the bandwidth of the amplifier stage. An increase inthe bandwidth has little effect, as will be seen later, however areduction in the bandwidth of the gain altering stage affects thebandwidth of the entire system. Reducing z to less than -0.7,therefore, reduces the overall bandwidth. Additionally, fromFig. 1,we note that changing z beyond f0.7 causes the systemgain to vary from the desired exponential characteristics. It,therefore, becomes necessary to use two stages of gain controlto achieve the necessary gain range.

Fig. 4shows a simplified circuit schematic for the completevariable gain amplifier. The first two stages of this circuitprovide the necessary gain variation. The third stage stabilizesthe common mode voltage, provides a relatively large fixeddifferential mode gain and also helps to stabilize the groupdelay through the amplifier. The third stage is followed by

two source follower stages to drive external loads of 5 pF,as in [2]. During normal operation the VGA will be followedby other on-chip circuitry, usually a detector, and the sourcefollower stages can be dropped. A careful look at the first twostages will show that they are vertically flipped mirror imagesof each other. For example, transistors Q7 and QS provide thesame functionality for the second stage as do transistors Q3and Q4 for the first stage. This allows the circuit topologyto be extended from one variable g i n stage to n variablegain stages, where the value of n is only limited by powerconsumption, circuit noise and the total phase contribution.Increasing the number of stages increases the range of gainvariability possible. For example, four such stages could beused to provide 60dB of gain variability.

As both the gain control stages operate similarly we willdiscuss only the first stage. Transistors Q3 and Q4 are diodeconnected and operate as the load transistors for the differentialpair Q1 and Q2. The gain for the first stage is controlledby the ratio of the transconductances of Q2 and Q4 (andQ 1 and Q 3) , {gainstagel= ( g r n 2 / g r n 4 ) } . The ratio of theirtransconductances can be varied by changing the ratio of thecurrents that pass through Q2 and Q4. The current flowingthrough Q2 and Q4 are given by

The gain of the first stage can therefore be altered bychanging the value of the current 11 nd is equal to

The left half of the gain expression given by (5) is a functionof device sizes and process parameters and is a constant duringnormal use. The right half has the form J(l + z)/(1- z). smentioned earlier, except for the square root this expressionhas the exact form we desire. To compensate for the squareroot we use two stages and vary the current I1 from -0.7Ibto +0.7Ib to achieve the necessary 30 dB of gain variation.Currently a simple class-A current amplifier is used to generatethe current I1. Alternately, a class-AB current amplifier design[9] can also be used and will further help reduce powerconsumption. However, care must be taken to reduce crossoverdistortion or VGA gain hunting is likely to occur.

The voltage sources (V , f f ) re included to allow the currentsources of the second and third stages to operate in thesaturation region. The value of 0.4 V for this offset voltageis selected such that it is greater than the (Vgs- &) of thecurrent sources but is small enough such that it does not havemuch impact on the input common mode range of the VGA.


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37 2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 42, NO . 6, JUNE 1995

, +&,

Fig. 4. Complete variable gain amplifier schematic.

Fig. 5.This offset voltage is generated using a feedback scheme thatprovides a low impedance voltage source and is shown in Fig.5. Fig. 6 shows the SPICE simulation results for the offsetvoltage generator. When the load current approaches 100 nAthe offset voltage rapidly rises to 0.4 V and then remains fairlysteady even when the load current increases to 100 P A . Ifcommon mode range is not of concern then a simple diodeconnected transistor can be used instead. Transistor Q 3 2 isoperated in the subthreshold region and transistors Q 3 1 , Q 3 3and Q 3 4 are operated in strong inversion. Transistor Q 3 4 isin the triode region and acts as a resistive load for transistorQ 32. The low resistance at this node is included to stabilizethe loop by increasing the pole frequency formed at the drainsof Q 3 2 and Q 3 4 . As soon as the gate to source voltage of Q 3 2is sufficiently large (approximately equal to V o f f )he draincurrent of Q 3 2 increases and pulls up the gate of transistorQ 3 3 . This in turn rapidly increases the gate to source voltage oftransistor Q31 and V o f f oes not increase beyond the desiredvalue. The circuit in Fig. 5functions in manner that is similarto a series voltage regulator except here we fix the voltagedrop across the load transistor rather than the output voltage.Since the necessary Awgs, (Augs = Vgs- G), s small theturn on voltage for transistor Q 3 3 is approximately equal toI& Using this constraint, the desired offset voltage, V o f f ,can be set using (6).

Circuit used to generate offset voltage.Fig. 6. Offset voltage versus load current.

Here UT is equal to KTIq which is approximately equalto 26mV at room temperature, the slope factor 17 is usuallybetween 1. 3 and 2 and is fairly controllable [lo], Kk is thetransconductance parameter for NMOS transistors, W32, L32 ,W 34 and L 3 4 are the widths and lengths of transistor Q 3 2and Q 34. Id 0 is a process dependent parameter and is highlyunpredictable. However, Id o affects the offset voltage onlylogarithmically such that a 100% variation in Id0 only causesa 6% variation in the offset voltage. The other parametersare likely to have much smaller variation. The loop gain forthe offset voltage generator with a load capacitance of 5 pFis shown in Fig. 7 and the closed loop source impedanceof the generator is shown in Fig. 8. The source impedanceof a diode connected, 1 lgm, transistor is also shown inFig. 8. We note that the source impedance for the offsetvoltage generator is lower than that for the diode connectedtransistor for low frequencies (36 0 s ) and increases at higherfrequencies. This results in a slight degradation of the CMRRat these frequencies. However, as mentioned earlier, the dcvoltage drop across the diode connected transistor is larger.

An expanded view of the third stage is shown in Fig. 9.Previously, transistors QII , Q12, Q15. &I69 Q19 and Q20were omitted from Fig. 4 for clarity. Transistors Q 1 5 andQ I S are identical in size to Q 9 and Q ~ ond are used tocancel the Miller multiplication effect. Transistors Q 1 9 andQ 2 0 are primarily included to reduce the negative feedbackeffect of the transistors Q 1 5 and QIS [141. However, they alsofunction to reduce the gate-to-source capacitive loading effectsof transistors and Q 1 6 . The third stage is set to have alarge gain as a result of which the drain-to-gate capacitance


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HARJANI: LOW-POWER CMOS VG A

30.Ee.5 0'1

-50 i

313

L

R q w y HZ 1101.a 103 la(h 1.M 1 1m

Fig. 8. Offset voltage generator source im pedance.

Fig. 9. Expanded view of the third stage.

Fig. 10.( c d s ) of Q9 and Qlo get Miller multiplied and lowers thebandwidth of the second stage. Traditionally, cascoding [5] isused to reduce the Miller multiplication effect. Unfortunately,cascoding also limits the maximum swing possible from theamplifier. For this reason we use the partial positive feedbackscheme to reduce Miller multiplication effects. A simplifiedschematic to calculate the effective gate referred capacitanceof the third stage is shown in Fig. 10.It can be shown that the

Simplified schem atic for capacitance calculation.

IFig. 1 1 . Simplified schematic for gain reduction calculation.

effective gate referred capacitance for this circuit is given by(7),where A is the gain of the third stage. When transistors Q9and Q15 are matched this equation can further be simplifiedto (8).

In comparison, the gate referred capacitance for the regularcascode technique is equal to 2Cgd + Cgs and the gatereferred capacitance for a noncascode noncanceled circuitis equal to Cgs + (1 + A)Cgd. Unlike normal cascodingtechniques, the addition of the two extra transistors Q15and Q ~ sncreases the gate-to-source capacitances slightly.However, the effect of this is much smaller than the effectcaused by Miller multiplication because of the large gainassociated with the third stage. For example, for our circuitfor a value of ll gdslg = 50K the effective gate referredcapacitance is only 12%larger than for a regular cascode. Asshown in (7) it is important that the two capacitances Cgdgand Cgdl5 match fairly well for complete cancellation. Thegate to drain capacitance is a function of the lateral diffusion ofthe drain junction and is highly process dependent. Therefore,it is important that identical methods be used to generate bothcapacitances. We use identical device sizes for this purpose.The drain-to-gate capacitances of transistors Q15 and Q16 areused to cancel the effects of the drain-to-gate capacitances ofQ9 and &io.Unfortunately, transistors Q15 and Q16 also provide nega-tive feedback which reduces the gain of the third stage. Forthis reason values for gdslg and gdsao are selected such thatthe transconductances of transistors Q15 and are muchsmaller than those of Q9 and & l o . Therefore, the gain is onlyreduced slightly. The resulting effective transconductance isgiven by (9). Since the sizes of Qg, & l o and &IS, Q~F arethe same their transconductance is set by the current flowingthrough them. The relationship between the currents troughQ9 and QIS are given by (10). For our design the reduction


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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11: ANALOG AND DIGITAL SIGNAL PROCESSING,VOL. 42, NO. 6, JUNE 199514

5.0

-i o-5.01

Fig. 12.

in the

Fr rquacy (&) \ ]Ih loMh I C " l.ffihBandwidth of the second stage with and without Miller cancellation.

transconductance is approximately four percent. Atextremely high frequencies the gain of the third stage becomessufficiently small due to its own bandwidth l imitations and theMiller multiplication effect becomes insignificant. In Fig. 12we plot the gain versus frequency for the second stage withand without our Miller cancellation circuit. The heavy lineshows the result after Miller effect cancellation and the thinline shows the result without any cancellation. In this figure wenote the reduction in gain due to Miller multiplication and alsothe reduction of this multiplication effect at higher frequencies.We also note that the plot is smoother after cancellation, i.e.more constant group delay. The Miller multiplication effecthas been canceled but there is a slight reduction in theoverall bandwidth due to the increase in the gate-to-sourcecapacitance. The transistors Q1 5 and Q l s primarily affect thehigh frequency ac behavior and so the overall circuit caneffectively be simplified by removing Q 1 5 , Q 1 6 , Q 1 9 and Q ~ oand assuming that the gate-to-drain capacitances of transistorsQ9 and Q ~ ore zero and that the effective transconductanceof Q15 and are reduced slightly.

The output stage is designed to provide a large bandwidthand large dynamic range at low distortion. This is achievedby using transistors Q1 1 and Q12 in the triode region. Twotransistors are used instead of one to cancel higher ordersignal distortion due to variations in threshold voltage as aresult of changes in the source to bulk voltage, (V sb ) of theload transistors. The circuit topology also allows for someindependent control of the differential mode and commonmode gain and bandwidths. The midpoint between the twotransistors is fairly constant for differential mode signals.Therefore, C, has no effect. However, for common modesignals C, acts as an additional load. Transistors Q13 and Q14provide common mode feedback and control the dc voltageat the outputs of the third stage. This topology for commonmode feedback [ll], [12] is particularly attractive for high

frequency applications and provides a number of advantageswhen compared to other topologies [121, [131. First, the circuitdoes not add any additional high impedance nodes in thecircuit that can add phase and affect the stability of thecommon mode feedback loop. Second, the two transistorsQ1 3 and Q1 4 operate in the triode region and provide alow impedance node at the source nodes of transistors Q17and Q18. The differential mode gain for this stage is set bythe triode operated transistors Q11 and Q1 Z and is given by(1 1). As mentioned earlier for differential mode signals C,has no effect. Additionally, for differential mode signals thecommon mode feedback circuit has no small-signal effect andthe impedance looking into the drains of Q17 and Q 1 8 arehigh. Therefore, the primary resistive load at the outputs isapproximately equal to the inverse of the conductance of Q1 1and Q 1 2 . Therefore, the bottom half of the circuit can bereplaced with a simple differential pair with zero gate to draincapacitance and slightly lower transconductance.

The common mode gain for a completely balanced circuitis ideally zero. However, any imbalance between the twosides results in some nonzero common mode gain. This isillustrated in Fig. 18. For this simulation the threshold voltageof transistor Q9 was altered by 1 0 m V . We note both a nonzerocommon mode gain and also the beneficial effect of addingC,. Though a complete analysis for common mode gainis not provided as this would entail listing the influence ofeach transistor in the third stage and all of their parameters.However, an qualitative explanation can be provided for theV t offset situation just mentioned. Other situations can beanalyzed similarly. The common mode gain for each halfof the circuit is given by the ratio of the conductancesg o / g l . Here g o is the conductance of the current source I Land gl is the effective conductance looking into the drainof transistor Q17 with the common mode feedback circuitbeing functional. The low frequency value of g l is given by( g m 1 7 g m l 3 ) / ( g d s l 3+ gm1 7 ) . The offset voltage is amplifiedby the gain of the third stage and causes the two outputvoltages to be different. This in turn causes the effective g lof the two halves to be different. The transconductance ofQ17, ( g m 1 7 ) , essentially remains the same because of theextremely small change in the current due to this change inthe output voltage. Likewise, the transconductance of Q13,gm 1 3 = l ( k k W / L ) V d s l 3 1 , also essentially remains the sameas the V d s is maintained constant by the common modefeedback effect. However, the conductance of Q13, gds13 =( k L W / L ) ( I V g s l 3 1 - IVt,l- I V d s 1 3 ( ) ,changes because V g s 1 3changes due to the difference in the two output voltages. Thiscauses the conductance looking into the drain of Q1 7 to bedifferent for that looking into the drain of & I S . Therefore, thegains of the two halves are not equal and this results in thenonzero common mode gain.

Due to the fully differential structure of the VGA anycommon mode signal at the input of the first stage is severely


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HARJANI: LOW-POWER CMOS VG A 375

attenuated by the first two stages before it gets to the out-put stage, i.e., the overall VGA has a fairly high commonmode rejection ratio (CMRR). Therefore, one of the primarypurposes of the common mode feedback circuit in the outputstage is to stabilize the output voltage in the face of process andtemperature variations. The primary source of such variationsare possible changes in the threshold voltages of the transistors,particularly those of Q9 and Q13. It also serves to rejectany other common mode signals that may arrive at the thirdstage via the supplies or the substrate. Additionally, because ofthe complete symmetry maintained throughout the design thepower supply rejection ratio is extremely high for this circuit.

The gain of the VGA is controlled by varying the current11. However, these variations in the current 11 affect thetransconductances of the differential pairs and diode connectedloads as well. This change in the load transconductances alsoaffects the bandwidth of the first two stages. To reduce theeffects of this change in bandwidth on the overall group delaythe bandwidths of the three stages are selected so that thebandwidth of the first two stages is much larger than thebandwidth of the third stage. Therefore, the bandwidth of theoverall amplifier is dominated by that of the third stage, whichis kept constant. One of our design goals is to maintain afairly constant group delay through the system. In general, thevariation in the group delay is minimized by maintaining thepoles close to the real axis. For a three stage system like oursthe delay through the system is given by (12). Here, w is thefrequency in radians and w1, w2 and w3 are the three systempoles. The variation in the group delay with frequency cannotbe made to be equal to zero for such a system. However, it canbe minimized within a frequency band by setting the valuesof w2 and w3 to be approximately equal to 2.23 times w1.This value was generated by settting w2 = w3 and finding theminimum of the derivative of (12). In our system, the thirdstage pole is selected to have the lowest frequency as thispole frequency does not change with gain settings. The polesof the other two stages are selected to be close to 2.23 timesthe third stage pole.

We shall see the effects of these and other design choicesin the results presented in the next section.

111. RESULTS AN D CONCLUSIONThe results presented in this section were generated with

the help of HSPICE simulations. Simulations were done usingboth BSIM and level 2 models. The results presented here areprimarily those from BSIM models. However, BSIM modelstend to be pessimistic about output conductance so resultswere also confirmed using level 2 models. Unfortunately, level2 simulations have the limitation that the transconductanceis discontinuous with respect to current. Layout parasiticestimates were also included in these simulations. These

Fig. 13. Amplifier gain in dB versus control voltage.

parasitic estimates were generated by completing a layout fora slightly earlier pass design using the Magic layout editor.The current circuit has been designed for the generic MOSIS2 micron process.

Three dB bandwidths greater than 85 MHz was achievedthroughout the gain range. Fig. 13 shows the gain in dBversus the control voltage and Fig. 14 shows the group delayat 50 MHz versus the control voltage for the variable gainamplifier. From Fig. 13 we find that we were able to generatethe desired exponential gain versus control voltage relation.Though we do achieve the 30 dB of variation we see somedeviations from the ideal exponential characteristics. We areable to obtain approximately 25 dB variation of gain along theideal exponential relationship. However, as mentioned earlier,this is an advantage rather than a disadvantage. The slightreduction in the overall gain range (from ideal exponentialgain to control voltage characteristics) as compared to theexpression described in (1) is due to channel modulation andother short channel effects not included in (1). These effectsreduce the effective transconductance for the transistors thatcontrol the gain in the first two stages. It is expected that theseminor variations from the ideal behavior, as long as they arenot abrupt, is unlikely to cause any major problems for theautomatic gain control loop. In Fig. 14 we find that the groupdelay is relatively constant with control voltage changes. InFig. 15 we show a 3 dB bandwidth of 109 MHz for a controlvoltage of 0.7 V. Fig. 16 shows the phase versus frequency forthe amplifier. To maintain a constant group delay through theamplifier it is necessary that the phase increase linearly withfrequency. In Fig. 16, we see that the phase increases linearlywith frequency till about 200 MHz which clearly suffices forour operating bandwidth. Fig. 17 shows the harmonic contentat the output of the amplifier for a 1.2VP-, output signal at5 0MH z . The first two stages use diode connected loads whichhave large quadratic nonlinearities. Additionally, each of thedifferential pairs generate quadratic nonlinearities. However,we note that the even harmonics are completely suppressedas might be expected in a fully differential design. The totalharmonic distortion for the overall amplifier was less than0.7% for a 1.2Vp-, output signal.

One of the primary advantages of generating the exponen-tial gain characteristic intrinsically, rather than use a lateralbipolar, is the reduction in power consumption. For exam-ple, the total power consumption for our VGA without thesource follower stages is approximately 10 mW. This isapproximately a order of magnitude lower than the power


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376 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11: ANALO G AND DIGITAL SIGNAL PROCESSING, VOL. 42, NO. 6. JUNE 1995

. . - .4M 0 1 0.5 0.8 1.1 1 1Fig. 14. Group delay versus control voltage.

- 1

F h u m a (Hr)40 \ ]1.m 1 1OMb 1.mFig. 15 . 3 dB frequency for amplifier.

Fig. 16. Acc umula ted phase for amplifier.

- - I ,/-I I I1.0mv-

Fig. 17.-30

-39 -501.

Fig. 18.

Total harmonic distortion of overall amplifier.

Ral-9 ow 1h Ion[h lOMh 1m

Effect of Cm on common mode gain.consumption for a variable gain amplifier that uses the parasiticlateral bipolar device [2]. And the power savings are even

larger in comparison to an all bipolar implementation [I].The current design has been designed to operate at 50 Mb/s.However, it is expected that the basic design can be extendedto higher frequencies by going to smaller geometries and/orby increasing the power. Additionally, a larger range in gainvariability can be accommodated by increasing the number ofof stages.

We have described a low-power CMOS variable gain am-plifier that uses only MOS devices to generate an exponentialgain versus control voltage characteristic necessary for readchannel electronics. This paper introduces a number of noveltechniques that are used to generate the exponential gainbehavior, increase bandwidth, provide a voltage drop less thanthe threshold voltage and stabilize the group delay.

REFERENCES[11 AD600/AD602 dual low-noise wideband variable gain amplifier,Analog Devices Data Sheet.[2] R. Gomez and A. A. Abidi, A 50 MHz variable gain amplifier cell in25 p m cmos, in CICC, 1991.[3 ] H. Sato, T. Okabe, K. Michii, and R. Sakano, Subsystem ics forWinchester disk drive, in IEEE Custom Integraf. CircuifsCon$, 1985.[4] AD890 precision, wideband channel processing element. Analog

Devices Data Sheet.[5] R. Gregorian and G. Temes, Analog MOS Integrated C ircuits fo r SignalProcessing. New York: Wiley, 1986.161 T.-W. Pan and A. A. Abidi, A variable gain amplifier using parasiticbipolar transistors in cmos, IEEE J. Sulid-Srute Circuils, vol. 24, Aug.1989.[7 ] K. Nagraj, New cmos floating voltage-controlled resistor, Electron.Lett., vol. 22 , 1986.[8] B. Nauta, E. Klumperink, a nd W. Kruiskamp, A cmo s triode transcon-ductance, in Inf. Symp. Circu ifs Sysr., IEEE, 1991, pp. 2232-2235.[9] 2.Wang, Wideband class AB (Push-Pull) current amplifier in cmostechnology, Electron. Let f . , pp. 543-545, Apr. 1990.[IO] E. C. Vittoz, Micropower Techniquesin Design of MOS V U1 Circuits orTe[ecommunications, Y . Tsividis and P. Antognetti, Eds. EnglewoodCliffs, NJ: Prentice-Hall, 1985, ch. 4.[ ll ] T. Choi, R. Kaneshiro, R. W. Broderson, P. R. Gray, W. Jett, and M.Wilcox, High-frequency cmos switched-capacitor filters for communi-cations applications, IEEE J. Solid-state Circuits, ol. 18, pp. 6526 64,1983.[I21 J. Duque-Camillo, Control of common-mode component in cmoscontinous-time fully differential signal processing, Analog IntegratedCircuits and Signal Processing. New York Kluwer Academic, 1993,pp. 131-140.[13] P. Wu, R. Schaumann, and P. Latham, Design considerations forcommon-mode feedback circuits in fully-differential operational ampli-fiers with tuning, in IEEE Int. Symp. Circuits Sysf . , pp. 1363-1366,1991.[I41 Z. Czamul and Y. Tsividis, MOS tunable transconductor, Electron.Lett., vol. 22, pp. 721-722, June 1986.

Ramesh Harjani (S87-M89) received the B.Tech,M.Tech, and Ph.D. degrees in electrical engineeringin 1982, 1984, and 1989 from Birla Institute ofTechnology and Science, Pilani, India, the IndianInstitute of Technology, New Delhi, and CamegieMellon University, Pittsburgh, PA, respectively.He was with Mentor Graphics Corporation, SanJose, CA, until 1990 when he joined the Depart-ment of Electrical Engineering at the Universityof Minnesota, Minneapolis, where he is currentlyemployed. His research interests include analogCAD techniques, low pow er analog design, disk drive electronics and analogand mixed-signal circuit test.Dr. Harjani received the National Science Foundation Research InitiationAward in 1991, and a Best Paper Award at the 1987 IEEWACM DesignAutomation Conference.

low power cmos vga

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