mpmc notes

8/11/2019 MPMC Notes

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PRAGATI ENGINEERING COLLEGE :: SURAMPALEMMICROPROCESSORS & MICROCONTROLLERS

1

Introduction: A digital computer is an interconnection of different digital modules.

Processor is the one which do operations.

Control unit issues the required control signals to perform specific task.

Processor combined with control unit often referred to as CPU (Central Processing Unit) or a CPU enclosed in a smallintegrated circuit package is known as microprocessor.

Fig: Block diagram of a digital computer

Number System:

Numbers can be expressed to any base.

- If base is 2 then those numbers are known as binary numbers. In these numbers individual digits are 0 & 1.

-

If base is 8 then those numbers are known as octal numbers. In these numbers individual digits vary from 0 to 7.- If base is 10 then those numbers are known as decimal numbers. In these numbers individual digits vary from 0 to

9.

- If base is 16 then those numbers are known as hexa decimal numbers.In these numbers individual digits vary from0 to 9, A,B,C,D,E OR F.

Any number in baser system can be converted to decimal using the formula

anrn+ an-1r

n-1+ an-2r

n-2+ ..+ a1r

1+ a0+ a-1r

-1+ a-2r

-2+ ..

Each HEX digit can be represented in binary using four bits.

Decimal Hex Binary

0 0 00001 1 0001

2 2 0010

3 3 0011

4 4 0100

5 5 0101

6 6 0110

7 7 0111

8 8 1000

9 9 1001

10 A 1010

11 B 1011

12 C 1100

13 D 1101

14 E 1110

15 F 1111

Processor Control Unit

Memory

Output

devices

Input

devices


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Evolution of Microprocessors:

- Worlds first microprocessor released by Intel Corporation is 4004. It is a 4-bit microprocessor. It can address to amemory of 4096 memory locations, each of 4- bits size. It has 45 instructions in its instruction set.

Note:

4-bit microprocessor means it can transfer 4-bits of information in parallel at a time. In other words its data bus is

of size 4-bits(D0-D3).

It can address to a memory of 4096 memory locations means its address bus is of size 12 bits(A0 -A11).

-

The evolution of 4-bit microprocessor ended when Intel released 4040, an updated version of 4004.

- In 1971, Intel Corporation released 8008 -an extended 8-bit version of 4004.The 8008 can address to a memory of 16Kbytes or it has 48 instructions in its instruction set.

- Small size, slow speed and limited instruction set are the general limitations in older version of microprocessors. Intelrecognized these limitations and in 1973, Intel released the first modern 8-bit p-8080.

- About 6 months after Intel recognized 8080, Motorola released MC6800 p. Some other companies like Zilog,Rockwell also started manufacturing their own versions of ps. Zilog still manufacturers of ps, but remained in

background, concentrating on microcontrollers and embedded controllers instead of general-purpose ps. Rockwellabandoned p development in favor of modem circuitry.

- In 1977, Intel released updated version of 8080-the 8085. This was the last general purpose p developed by Intel.Intel has sell over 100 million copies of 8085 ps and is the most successful general purpose 8-bit p .

- In 1978, Intel released the 8086 p. It is the first 16-bit general purpose p which can address upto 1M bytes ofmemory. Concept of memory segmentation was introduced in 8086 p.

- In 1979 Intel released 8088 microprocessor, which has 8-bit data bus and which can address 1M byte of memory.- In 1983, Intel released 80286, which has the combined features of both 8086 OR 8088. It can address 16 M bytes of

memory. The clock speed of 80286 is increased sothat it can execute instructions in 250ns (4.0 MIPS) with original8.0 MHz clock.

- Applications demand faster p speeds, more memory and wider data paths. This led to 80386 in 1986. 80386 wasIntels first practical 32-bit p which has 32-bit data bus OR 32-bit address bus. It can address upto 4G bytes ofmemory.

- In 1989, Intel released 80486 p. It has an 80386-like microprocessor and an 80387-like numeric co-processor and an8K byte cache memory system into one integrated circuit package. 80486 was available in 50 MHZ version.

Note:

Concept of Cache memory is introduced from 80486. Cache memory is placed between main memory and CPU. It can be accessed by the CPU at a faster rate than the

main memory. It is very costly.

- In 1993 Intel introduced Pentium, which was similar to 80386 and 80486.The two introductory versions of Pentiumare available with a clock frequency of 60 MHZ and 66 MHZ and at a speed of 110 MIPS , with higher frequency of100 MHZ that operated at 150 MIPS.The most important feature of Pentium is its dual integer processors. Pentium executes two instructions, which are

independent on each other simultaneously. Because it contain two independent internal integer processors, calledSuperscalar technology.

- Later Intel Corporation released Pentium pro, Pentium-II, Pentium-II Xeon, Pentium-III and Pentium-IVmicroprocessors. These processors have 64 bit data bus width and 64GB addressable memory.

-

MicroprocessorsYear of

Introduction

Word

Length

Memory

AddressingPins Clock Remarks

4004 1971 4 bits 1KB 16 750KHz Intels 1st P

8008 1972 8 bits 16KB 18 800KHzMark-8 used this;1st computer for the home

8080 1973 8 bits 64KB 40 2 MHz 6000trs, Altair-1st PC

8085A 1976 8 bits 64KB 40 3-6 MHz Popular

8086 1978 16 bits 1 MB 40 5-10 MHzIBM PC, Intel became

one of fortune 500companies.

8088 1980 8/16 bits 1MB 40 5-8MHz PC/XT

80186 1982 16 bits 1 MB 68 5-8MHz More a Microcontroller


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Fig(c) Pentium Pro Fig (d) Pentium II, Pentium III, Pentium IV

***

Memory Segmentation:

The memory in an 8086/8088 based system is organized as segmented as segmented memory. In this scheme , thecomplete physically available memory may be divided into a number of logical segments. Each segment is 64k bytes in sizeOR is addressed by one of the segment registers. The 16-bit contents of the segment register actually point to the startinglocation of a particular segment. To address a specific memory location within a segment , we need an offset address. The

offset address is also 16-bit long so that the maximum offset value can be FFFFH, OR the maximum size of any segment isthus 64K locations.

The CPU 8086 is able to address 1 Mbytes of physical memory . The complete 1 Mbytes memory can be dividedinto 16 segments , each of 64Kbytes size. The address of the segments may be assigned as 0000H to F00H respectively. Theoffset address values are from 0000H to FFFFH so that the physical addresses range from 00000H to FFFFFH.

The main advantages of the segmented memory are

1. Allows the memory capacity to be 1Mbytes although the actual addresses to be handled are of 16-bit size.2.

Allows the placing of code, data and stack portions of the same program in different parts (segments) of

memory ,for data and code protection.3. Permits a program and/or its data to be put into different areas of memory each time the program is executed

,i.e. provision for relocation is done.

Physical Address:The 20- bit address of any memory location in 1MB of memory, which can be addressed by 8086 is called Physical

address.

Offset Address:Displacement of any memory location from the starting of the segment is called Offset address

Effective Address:Effective Address = Offset Address + Displacement, if any

Segment Base:

The most significant 16-bits of the starting address of any Segment is called Segment Base.Note:

1.

Code Segment register contain Code Segment base.

2. Data Segment register contain Data Segment base.3.

Extra Segment register contain Extra Segment base.4.

Stack Segment register contain Stack Segment base.

Calculation of Starting Address of a Segment:To get Starting Address of any Segment, append 4-binary zeros (or) one HEX zero as least significant digit to the Segment

Base .

Therefore,Physical address= Starting address of the Segment + Effective address

16K L1 Cache

256K L2 Cache

C

P

U

C

P

U

3

C

O

P

R

O

C

P

U

232K L1 Cache

256K (or) 512K L2 Cache

C

P

U

1

C

P

U

2

C

P

U

3

C

0

P

R


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Fig: One way of positioning four 64-Kbyte segments within the 1-Mbyte address space of 8086

In the Overlapped Area Locations, Physical Address = CS1+IP1 = CS2+IP2 ,where + indicates the procedure of physicaladdress formation.

5FFFFH

70000H

7FFFFH

FFFFFH

PHYSICAL

ADDRESS MEMORY

EXTRA SEGMENT BASE

ES=7000H

HIGHEST ADDRESS

TOP OF EXTRA SEGMENT

STACK SEGMENT BASE

SS = 5000H

TOP OF CODE SEGMENT

TOP OF STACK SEGMENT

CODE SEGMENT BASE

CS=348AH

TOP OF DATA SEGMENT

BOTTOM OF DATA SEGMENT

64K

64K

64K

64K

50000H

4489FH

348A0H

2FFFFH

20000H


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Fig:Addition of IP to CS to produce the physical address of the code byte

Fig : Non-overlapped Segments

Fig : Overlapped Segments

348A0H

38AB4H

4489FH

PHYSICAL

ADDRESS

MEMORY

CODE BYTE

TOP OF CODE SEGMENT

START OF CODE SEGMENTCS=348AH

IP=4214H


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Generation of Physical address:

The 8086 microprocessor has 20 bit address pins. These are capable of addressing 220= 1Mega Byte memory. To generate

this 20 bit physical address from 2 sixteen bit registers, the following procedure is adopted.

The 20 bit address is generated from two 16-bit registers. The first 16-bit register is called the segment base register. These

are code segment registers to hold programs, data segment register to keep data, stack segment register for stack operations

and extra segment register to keep strings of data. The contents of the segment registers are shifted left four times withzeroes (0s) filling on the right hand side. This is similar to multiplying four hex numbers by the base 16. This

multiplication process takes place in the adder and thus a 20 bit number is generated. This is called the base address. To

this a 16-bit offset is added to generate the 20-bit physical address.

Segmentation helps in the following way. The program is stored in code segment area. The data is stored in data segment

area. In many cases the program is optimized and kept unaltered for the specific application. Normally the data is variable.

So in order to test the program with a different set of data, one need not change the program but only have to alter the data.

Same is the case with stack and extra segments also, which are only different type of data storage facilities.

Generally, the program does not know the exact physical address of an instruction. The assembler, a software which

converts the Assembly Language Program (MOV, ADD etc.) into machine code (3EH, 4CH etc) takes care of address

generation and location.

Example1:Segment base value in CS = 348AH20- bit starting address of code segment = 348A0H

(It is shifted by one position OR LSB is loaded with zeros)16 -bit EA or offset in IP = 4214HThe 20- bit physical address of 38AB4H is quite often represented in segment based, offset form as 348A:4214, as this fromclearly indicate the segment base value OR the EA.

In an 8086 based system , the 1Mbyte of memory organized as odd bank and even bank , each of 512k bytes ,addressedin parallel by the processor .Byte data with even address is transferred on D7-D0, while the byte data with odd address is

transferred on D15-D8 bus lines. The processor provides two enable signals, BHE and A0 for selection of either even orodd or both the banks.

In referring word data , the BIU requires one or two memory cycles, depending upon whether the starting byte is locatedat an even or odd address .It is always better to locate the word data at an even address. To read or write a complete wordfrom/or to memory, if it is located at an even address , only one read or write cycle is required . If the word is located at an

odd address , The first cycle is required for accessing the lower byte while the second one is required for accessing the upperbyte. Thus two bus cycles are required , if a word is located at an odd address.

8086 Memory Addressing :

The 8086 memory address space can be viewed as a sequence of one million bytes in which any byte may contain an 8-bit data element and any two consecutive bytes may contain a 16-bit data element. There is no constraint on byte or wordaddress boundaries. The address space is physically connected to a 16-bit data bus by dividing the address space into two 8-

bit banks of up to 512K bytes each.One bank is connected to the lower half of the 16-bit data bus (D0D7) and contains even address bytes. i.e., when A0

bit is low, the bank is selected. The other bank is connected to the upper half of the data bus (D8 - D15) and contains odd

address bytes. i.e.,when A0 is high and BHE (Bus High Enable) is low, the odd bank is selected. A specific byte withineach bank is selected by address lines A1-A19.


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HigherAddress

Bank(512K x 8)

ODD

LowerAddress

Bank(512K x 8)

EVEN

A1-A19

Address Bus

Data Bus (D0 - D15)

D8-D15 D0-D7

BHE A0

Fig. Organization of 1 Mega byte of memory in 8086

Data can be accessed from the memory in four different ways. They are:

8 - bit data from Lower (Even) address Bank.

8 - bit data from Higher (Odd) address Bank.

16 - bit data starting from Even Address.

16 - bit data starting from Odd Address.

8-bit data from Even address Bank :

A1-A19

D0-D15

BHE = 1

D8-D15 D0-D7

A0 = 0

x

x + 2

x + 4

x + 1

x + 3

x + 5

Odd Bank Even Bank

Fig. 8-bit data access from an even address

To access memory bytes from Even address, information is transferred over the lower half of the data bus (D0- D7).

The A0 is output LOW and BHE is output HIGH enabling only the even address bank. It is illustrated in fig. 6.

Example:Consider loading a byte of data into CH register (higher order 8-bits of CX register) from the memory location with

an even address. The data will be accessed from the even bank via the (D0 - D7) DATA BUS. Although this data istransferred into the 8086 over the lower 8-bit lines, the 8086 automatically redirects the data to the higher 8-bits of its internal16-bit data path and hence to the CH-register. This capability allows bytes input - output transfer via the AL register to accessI/O device connected to either the upper half of the data bus or the lower half of the 16-bit data bus.

8-bit Data from Odd Address Bank:

To access memory byte from an odd address information, is transferred over the higher half of the data bus (D8 -

D15). The BHE output low enables the upper memory bank. A0 is output high to disable the lower memory bank. It isshown in the following figure.

A1-A19

D0-D15

BHE =0 A0 = 1

x

x + 2

x + 1

x + 3

Odd Bank Even Bank

D8-D15

D0-D7


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Fig. 8-bit data access from an Odd address

16-bit Data Access starting from EvenAddress:

A1-A19

D0-D15

BHE =0A0 = 0

x

x + 2

x + 1

x + 3

Odd Bank Even Bank

D8-D15

D0-D7

Fig. 16-bit data access from an Odd address

16-bit data from an even address is accessed in a single bus cycle. Address lines A1 - A19 select the appropriatebyte within each bank. A0 low and BHE low enables both banks simultaneously. This is shown in the above figure.

16-bit Data Access starting from Odd Address:

A 16-bits word located at an odd address (two consecutive bytes with the least significant byte at an odd byteaddress) is accessed using two bus cycles. During the first bus cycle the lower byte (with the odd address 0005H ) isaccessed.

A1-A19

Odd Bank Even Bank

D8-D15D0-D7

A1-A9

0005

00070009

0004

0006

0008

A1-A19

Odd Bank Even Bank

D8-D15D0-D7

A1-A9

0005

00070009

0004

0006

0008

(a) First Access from Odd Address (b) Next Access from Even Address Fig.

During the second bus cycle, the upper byte (with the even address 0006H as in fig. 9 (b)) is accessed. During the

first bus cycle, A1 - A19 address bus specifies the address and A0 as 1 and BHE is low. Therefore the even memory bank isdisabled and odd memory bank is enabled. During the second bus cycle, the address is incremented. Therefore A0 is zero

and BHE is made high. The even memory bank is enabled and the odd memory bank is disabled.

ADDRESS DATATYPE BHE A0 BUS CYCLES DATALINESUSED

0000

0000

0001

0001

BYTE

WORD

BYTE

WORD

1

0

0

0

1

0

0

1

1

0

ONE

ONE

ONE

FIRST

SECOND

D0-D7

D0-D15

D7-D15

D7-D15

D0-D7

1.Certain locations in memory are reserved for specific CPU operations. The many locations from FFFF0H to FFFFFH arereserved for operations including jump to initialization

2.

The locations 00000H to 003FFH are reserved for interrupt vector table.


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***Addressing Modes of 8086:

Different ways of addressing the operands to access the data, which is required to execute the instructions are knownas addressing modes.I.

Immediate addressing mode:

Ex: MOV AX, 1234HAbove instruction copies the immediate word 1234H into the register AX.In the above instruction, source operand is specified using Immediate addressing mode.

II.

Register addressing mode:Ex: MOV AX, BXAbove instruction copies the word in BX to the register AX.In the above instruction, source and destination operands are specified using Register addressing mode.

III. Memory Addressing mode:a)

Direct Memory addressing:If the offset address of the memory location is specified directly in the instruction itself then it is called Direct

Memory addressing.Ex: MOV AX, [1234H]Above instruction copies the word from the memory location whose offset address is 1234H into the register AX.

In the above instruction, source operand is specified using Direct memory addressing mode.

b)

Indirect Memory addressing:

If the offset address of the memory location is specified in an indirect way then it is called Indirect Memoryaddressing.

(i)

Register Indirect addressing:If the offset address of the memory location is specified using a register then it is called Register Indirect

Memory addressing.Ex: MOV AX, [BX]Above instruction copies the word from the memory location whose offset address is content of BX to the register

AX.In the above instruction, source operand is specified using Register Indirect memory addressing.

(ii)

Based addressing with displacement:If the offset address of the memory location is specified using one of the base register and displacement

then it is called Based addressing with displacement.Ex: MOV AX, 1234H[BX]

Above instruction copies the word from the memory location whose offset address is [BX] + 1234 H into theregister AX.In the above instruction, source operand is specified using Based addressing with displacement mode ofaddressing.

(iii)

Indexed addressing with displacement:

If the offset address of the memory location is specified using one of the Index register and displacementthen it is called Indexed addressing with displacement.Ex: MOV AX, 1234H[SI]

Above instruction copies the word from the memory location whose offset address is [SI] + 1234 H into theregister AX.In the above instruction, source operand is specified using Indexed addressing with displacement mode of

addressing.(iv)

Based Indexed addressing:

If the offset address of the memory location is specified using one of the Base register and one of theIndex register then it is called Based Indexed addressing.

Ex: MOV AX, [BP][DI]Above instruction copies the word from the memory location whose offset address is [BP] + [DI] to the registerAX.In the above instruction, source operand is specified using Based Indexed addressing.

(v)

Based Indexed addressing with addressing:If the offset address of the memory location is the sum of the content of one of the Base register,one

of the Index register and displacement then it is called Based Indexed addressing with displacement.

Ex: MOV AX, 1234H[BX][DI]Above instruction copies the word from the memory location whose offset address is [BX] + [DI]+ 1234 H to theregister AX.

In the above instruction, source operand is specified using Based Indexed addressing with displacement.

IV.

I/O Port addressing:a)

Fixed Port addressing:If Port address is specified directly in IN/OUT instruction, then it is called Fixed Port addressing.Ex: IN AL,55HAbove instruction reads a byte from the port whose address is 55H to AL.


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The Bus Interface Unit consists of segment registers, adder to generate 20 bit address and instruction pre-fetch andqueue. Once this address is sent out of BIU, the instruction and data bytes are fetched from memory and they fill a First InFirst Out 6- byte long queue.

The Queue:

While the EU is decoding an instruction or executing an instruction which does not require use of the buses, the BIU

fetches up to six instruction bytes for the following instructions. The BIU stores these pre fetched bytes in a first-infirst- outregister set called a queue. When the EU is ready for its next instruction, it simply reads for its next instruction, it simplyreads the instruction bytes for the instruction from the queue.

To speed up program execution, the BIU fetches as many as 6 insturction bytes ahead of time from memory. The

prefetched instruction bytes are held for the EU in a first-in-first-out group of register called a queue. The EU decodes aninstruction or executes an instruction which does not require the buses. When the EU is ready for its next instruction, itsimply reads the instruction from the queue in the BIU. Fetching thenext instruction while the current instruction executes, is called pipelining.

Note: The 8088 microprocessor has only a 4-byte queue.

Instruction Pointer (IP):

The Instruction Pointer is a 16-bit register. This register is always used as the effective memory address, and is

added to the Code segment with a displacement of four bits to obtain the physical address of the opcode. The code segmentcannot be changed by the move instruction. The instruction pointer is incremented after each opcode fetchto point to the next instruction.

Segment Registers:

The 8086 / 8088 microprocessor has 20-bit address lines. All the registers in 8086 / 8088 are 16-bits in length.Hence to obtain 20-bit addresses from the available 16-bit registers, all 8086 / 8088 memory addresses are computed bysumming the contents of a segment register and effective memory address. The effective memory address is computed via a

variety of addressing modes. The process of adding, to obtain 20-bit address is as follows:The selected segment register contents are shifted-left four bits (i.e., the contents are multiplied by 16 decimal), and

then added to the effective memory address to generate the actual physical address output.

Segment Register value

i.e., Segment Base( CS, DS, ES or SS)

x x x x x x x x x x x x x x x x

Starting address of the segment x x x x x x x x x x x x x x x x 0 0 0 0

Effective Memory Address y y y y y y y y y y y y y y y y

Physical Address wwww wwww wwww wwww wwww

Table

The table shows 16-bits of the segment registers CS, DS, ES or SS displaced by 4-bits to the left. The effectiveaddress is calculated depending on the type of addressing mode. The effective address is shown as yyyyyyyy yyyy yyyy.The 20-bit physical address wwwwwwww wwww wwww wwww is obtained after adding the segment register value andeffective address. The physical address is 20-bits wide.

To understand how the segmentation is used, it is required to know the memory structure of the 8086 / 8088microprocessor.

The memory in an 8086/8088 system is a sequence of up to 220= one million bytes. A word is any two consecutive

bytes in memory (word alignment is not required). Words are stored in memory with the most significant byte at the highermemory address. These bytes are stored sequentially from byte 00000 to byte FFFFF hex.

Programs view memory space as a group of segments defined by the application. A segment is a logical unit of

memory that may be up to 64K bytes long. Each segment is made up of contiguous memory locations and is an independent,separately addressable unit. Each segment is assigned a base address, which is its starting location in the memory space. Allsegments start on 16-bit memory boundaries. Segments may be adjacent, disjoint, partially overlapped, or fully overlapped.It is as shown in figure below.

The segment registers point to the four immediately addressable segments. The four segment registers are

Code Segment register [points to the instruction opcode]

Data Segment register [points to the data memory]

Stack Segment register [points to the Stack memory] Extra Segment register [points to the data memory]


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0 10000h 20000h 30000h

Segment A Segment B

Segment C

Segment D

Segment E

Contiguous memory

Fully overlap

Disjoint

Partial overlaped

The segment registers and their default offsets are given below.

Segment Register Default Offset

CS IP (Instruction Pointer)

DS SI, DI

SS SP, BP

ES DI

FFFFFH

A

B

C

D

E

F

G

IH

J

00000H

CS

DS

SS

ES

Above figure shows the segment registers pointing to the various memory segments. Since logical addresses are 16-bits wide, up to 64K (65536) bytes in a given segment can be addressed.

Each time the CPU need to generate a memory address, one of the segment registers is automatically chosen and its

contents added to a logical address.For an instruction fetch, the code segment register is automatically added to the logical address (in this case, the

contents of the instruction pointer) to compute the value of the instruction address.

For stack referencing the stack segment register is automatically added to the logical address (the SP or BP register

contents) to compute the value of the stack address.For data reference operations, where either the data or extra segment register is chosen as the base, the logical

address can be made up of many different types of values: it can be simply the immediate data value contained in the

instruction, or it can be the sum of an immediate data value and a base register, plus an index register. Generally, theselection of the DS or ES register is made automatically, though provisions do exist to override this selection. Thus anymemory location may be addressed without changing the value of the segment base register. In systems that use 64K or

fewer bytes of memory for each memory area (code, stack, data and extra), the segment registers can be initialized to zero atthe beginning of the program and then ignored, since zero plus a 16-bit offset yields a 16-bit address. In a system where thetotal amount of memory is 64K bytes or less, it is possible to set all segments equal and have fully overlapping segments.

Segment registers are also very useful for large programming tasks, which require isolation of program code from

the data area, or isolation of module data from the stack information etc.Segmentation makes it easy to build re-locatable and reentrant programs. In many cases, the task of relocating a

program (relocation means having the ability to run the same program in several different areas of memory without changing

addresses in the program itself) simply requires moving the program code and then adjusting the code segment register topoint to the base of the new code area. Since programs can be written for the 8086 / 8088 in which all branches and jumpsare relative to the instruction pointer, it does not matter what value is kept in the code segment register. Every applicationwill define and use segments differently. The currently addressable segment override provide, a generous workspace: 64K

bytes for code, 64K bytes stack and 128K bytes of data storage.


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Solved Problems

1. If a physical branch address is 5A230 H when (CS) = 5200 H, what will it be if the (CS) are changed to 7800 H.CS: 52 0 0

Offset: XXXX

Physical add. 5A2 3 0 HHence Offset = Physical add - (Segment address displaced by 4-bits)

Offset = 5A230 - 52000 = 8230 H

If the CS is changed to 7800 H the Physical address will be 78000 + 8230 = 802302. Given that the EA of a datum is 2359 H OR the DS = 490B H, what is the physical address of the datum?

DS: 490B0 HEA: 2359 H

Physical add. 4B409H

Execution Unit (EU):The execution unit consists of

1.

General Registers

2. Arithmetic Logic Unit3.

Control unit4.

Flag Registers

The execution unit and the Bus Interface unit operate asynchronously. The EU waits for the instruction object codeto be fetched from the memory by the BIU.

The BIU fetches or pre-fetches the object code (16-bits at a time) and loads it into the six bytes queue. Wheneverthe EU is ready to execute a new instruction, it fetches the instruction object code from the front of the instruction queue andexecutes the instruction in specified number of clock periods.

If memory or Input/output devices must be accessed in the course of executing an instruction, then the EU informsthe BIU of its needs. The BIU completes its operation code (opcode) fetch cycle, if in progress, and executes an appropriateexternal access machine cycle in response to the EU demand.

The BIU is independent of the EU and attempts to keep the six-bytes queue filled with instruction object codes. Iftwo or more of these six bytes are empty, then the BIU executes instruction fetch machine cycles as long as the EU does nothave an active request for the bus access pending. If the EU issues a request for the bus access while the BIU is in the middleof an instruction fetch machine cycle, then the BIU will complete the instruction fetch machine cycle before honoring the EU

bus access request.

The EU does not use machine cycles; it executes instructions in some number of clock periods that are not subjectedto any type of machine cycles. The only time clock periods are grouped is clock when the bus control logic wishes to access

memory or I/O devices.

General Registers

The CPU has eight 16-bit general registers. They are divided into two files of four registers each. They are:(a) The data register file and(b) The pointer and index register file

AX

BX

CX

DX

ALAH

BLBH

CLCH

DLDH Fig. Data Register File

AX, BX, CX OR DX registers are the data registers. The upper and lower halves of the data registers areindividually addressable. AX register can be addressed as AL and AH registers, BX register can be addressed as BL and BH

register, CX register can be addressed as CL and CH register, DX register can be addressed as DL and DH.The data registers can be used in most arithmetic and logic operations. Some instructions however require these

registers for specific use. This implicit register usage allows a more compact instruction encoding. Fig.1.4 shows the dataregisters specific one. The index register file consists of the Stack Pointer (SP), the Base Pointer (BP), Source Index (SI) and

Destination Index (DI) registers all are of 16-bits. They can also be used in most arithmetic and logic operations. Theseregisters are usually used to hold offset addresses for addressing within a segment. Offset addressing reduces program size byeliminating the need for each instruction to specify frequently used addresses.

The pointer and index register files are further divided into the pointer sub-file (containing the Stack Pointer and theBase Pointer registers) and the index sub-file (containing the Source index and Destination index registers). The Pointer

registers are used to access the current stack segment. The index registers are used to access the current data. (Stack segmentand data segment are specific areas of memory. Their application will be explained in later chapters). Unless otherwisespecified in the instruction, stack pointer registers refer to the current stack segment while index register refers to the current

data segment.


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The BP and SP registers are both used to point to the stack, a linear array in the memory used for subroutineparameters, subroutine return addresses, and the data temporarily saved during execution of a program

The implicit register usage is as follows:

AX Register Word MultiplicationWord Division andWord I/O Operation.

AL Register Byte MultiplicationByte DivisionByte I/OTranslate, and

Decimal Arithmetic

AH Register Byte Multiplication

Byte Division.

BX Register Base RegisterTranslate

CX Register String Operations

CL Register Variable Shift OR Rotate

DX Register Word Multiplication, WordDivision,Indirect I/O.

Fig.Most microprocessors have a single stack pointer register called the SP. 8086 / 8088 has an additional pointer into

the stack called the BP register. While the SP is used similar to the stack pointer in other machine (for pointing to subroutineand interrupt return addresses), the BP register is used to hold an old stack pointer value, or it can mark a place in thesubroutine stack independent of the SP register. Using the BP register to mark the stack saves the juggling of a single stackpointer to reference subroutine parameters OR addresses.

SI OR DI are both 16-bits wide and are used by string manipulation instructions and in building some of the morepowerful 8086/8088 data structures and addressing modes. Both the SI and the DI registers have auto incrementing and auto-decrementing capabilities.

IP

SR

DI

SI

BP

SP

DX

CX

AX

BX

ES

SS

DS

CS

Instruction Pointer

Code Segment Register

Data Segment Register

Stack Segment Register

Extra Segment Register

AH

Stack Pointer Register

AL

BE BL

CE CL

DH DL

Break Pointer Register

Source Index Register

Destination Index Register

Status Register

Code Segment (64Kb)

Data Segment (64Kb)

Stack Segment (64Kb)

Extra Segment (64Kb)

FFFFF16

00000016

8086/8088 MPU MEMORY


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Arithmetic Logic Unit (ALU)

ALU is 16-bits wide. It can do the following 16-bits arithmetic operations(i)

Addition(ii)

Subtraction

(iii) Multiplication(iv) Division

Arithmetic operations may be performed on four types of numbers

Unsigned binary numbers

Signed binary numbers (Integers) Unsigned packed decimal numbers

Unsigned unpacked decimal numbersThe ALU can also perform logical operations such as

(i) AND(ii)

OR

(iii) NOT(iv) EXCLUSIVE OR(v) TEST

The Arithmetic and Logic Unit adjacent to these registers perform all the operations. The results of these operations can

affect the condition flags.

Control Circuitry:

Generation of 20-bit Physical Address:

Flag Register:A flag is a flip-flop which indicates some condition produced by the execution of an instruction or controls certain operations

of the EUThe six conditional flags in the flag register are

Carry flag(CF)

Parity flag(PF)

Auxiliary Carry flag(AF)

Zero flag(ZF)

Sign flag(SF) Overflow flag(OF)

The three remaining flags in the flag register are control certain operations of the processor.The three control flags are the trap flag(TF), which is used for single stepping through a program; the

interrupt flag(IF),which is used to allow or prohibit the interruption of a program; and the Direction flag(DF), which is used

with string instructions.

LOGICAL ADDRESS

SEGMENT REGISTER 0000

ADDER

20 BIT PHYSICAL MEMORY ADDRESS


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Conditional Flags:

Carry Flag (CF)

This flag will be set to one if the addition of two 16-bit binary numbers produces a carry out of the most significantbit position or if there is a borrow to the MSB after subtraction. This flag is also affected when other arithmetic and logical

instruction are executed.

Parity Flag (PF)

This flag is set, if the result of the operation has an even number of 1's (in the lower 8 bits of the result). This flag

can be used to check for data transmission error.

Auxiliary Carry Flag (AF)

This flag is set, when there is a carry out of the lower nibble to the higher nibble or a borrow from the higher nibbleto the lower. The auxiliary carry flag is used for decimal adjust operation. The AF flag is of significance only for byte

operations during which the lower order byte of the 16-bit word is used.

Zero Flag (ZF)

This flag is set when the result of an operation is zero. The flag is reset when the result is not zero.

Overflow Flag (OF)This flag is set, when an arithmetic overflow occurres. Overflow means that the size of the result exceeded the

storage capacity of the destination, and a significant digit has been lost.

(a) : CARRY FLAGSET BY CARRY OUT OF MSB

(b): PARITY FLAGSET IF RESULT HAS EVEN PARITY

(c) : AUXILIARY CARRY FLAG FOR BCD

(d): ZERO FLAGSET IF RESULT = 0

(e) : SIGN FLAG = MSB OF RESULT

(f) : SINGLE STEP TRAP FLAG

(g)

: INTERRUPT ENABLE FLAG

(h): STRING DIRECTION FLAG

i : OVERFLOW FLAG

(i)

(h)

(g)

f

(e)

d

b

c

(a)

0123456789101112131415

U U U U 0F DF IF TF SF ZF U AF U PF U CF

U= UNDEFINED

BIT


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Sign Flag (SF)

This flag is set, when an MSB bit of the result is high after an arithmetic operation. When this flag is set the data in

assumed to be negative and when this flag is zero it is assumed to be positive.

Control Flags:

Control flags are used to control certain operations of the processor. The application of these flags are different

from that of six conditional flags. The conditional flags are set or reset by the EU on the basis of the result of somearithmetic or logic operations. The control flags are deliberately set or reset with specific instructions included in theprogram.

Trap flag (TF)This is used for single stepping through a program. It is used for debugging the programs. (Discusses with

interrupts).

Interrupt Flag (IF)It is used to allow / prohibit the interruption of a program. When the flag set, it enables the interrupt from INTR.

When the flag is reset (0), it disables the interrupt.

Direction Flag (DF)It is used for string instructiion (Discussed with the specific instructions later inthe book). If the direction flag is

set, the pointers are decremented else the pointers areincremented.

There are three internal buses, namely A bus, B bus and C bus, which interconnect the various blocks inside 8086.

The execution of instruction in 8086 is as follows:The microprocessor unit (MPU) sends out a 20-bit physical address to the memory and fetches the first instruction of a

program from the memory. Subsequent addresses are sent out and the queue is filled upto 6 bytes. The instructions aredecoded and further data (if necessary) are fetched from memory. After the execution of the instruction, the results may goback to memory or to the output peripheral devices as the case may be.

Instruction Set of 8086:I. Data Transfer Instructions: MOV,PUSH,PUSHF,POP,POF,XCHG,XLAT,LEA,LDS,LES,LAHF,SAHF,IN & OUT

II. (a) Arithmetic Instructions: ADD, ADC, INC ; SUB,SBB,CMP,NEG ; MUL,IMUL ; DIV, IDIV ; CBW, CWD(b) Logical Instructions: AND, OR, NOT, XOR, TEST

(c) Shift Instructions: SAL/SHL, SAR, SHR

(d) Rotate Instructions: ROL, ROR, RCL, RCR(e) String Instructions:

MOVS/MOVSB/MOVSW, CMPS/CMPSB/CMPSW, SCAS/SCASB/SCASW, LODS/LODSB/LODSW,STOS/STOSB/STOSW

(f) Repeat : REP/REPE(or)REPZ/REPNE (or) REPNZ

III. Program Control Instructions:(a)

Unconditional Jump Instructions: JMP,CALL, RET(b) Conditional Jump Instructions:

JAE/JNB, JA/JNBE, JB/JNAE, JBE/JNA,JGE/JNL, JG/JNLE, JL/JNGE, JLE/JNG,JC,JNC,JP/JPE,JNP/JPO,JE/JZ,JNE/JNZ, JS,JNS,JO,JNO

(c) Iteration Control Instructions:LOOP/LOOPE (or) LOOPZ/ LOOPNE (or) LOOPNZ, JCXZ

IV. Some other Instructions:

(a) Flag set/Reset Instructions: STC,CLC,CMC ; STD,CLD ; STI,CLI(b)

External Hardware Synchronization Instructions: LOCK, WAIT, HLT, NOP(c)

Decimal Adjust Instructions: AAA,AAS,AAM,AAD,DAA

***


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I. Data Transfer Instructions: MOV,PUSH,PUSHF,POP,POF,XCHG,XLAT,LEA,LDS,LES,LAHF,SAHF,IN & OUT

MOV (Copy a byte/ word)MOV Destination, SourceMOV instruction is used to copy a byte/word from the specified source to the specified destination. Source can be an

immediate number (or) a register (or) a memory location that can be addressed by anyone of the 24 addressing modes.Destination can be a register (or) a memory location that can be addressed by anyone of the 24 addressing modes.Note:

1. Both Source and Destination should not be two memory locations.

PUSHPUSH SourcePUSH instruction decrements the Stack Pointer (SP) register by two and it pushes the word from the specified source to the

memory location(s) now pointed to by SP. Source can be a register (or) a memory location that can be addressed by anyoneof the 24 addressing modes.Note:

1.Stack: Stack is a section of memory set aside to store data and addresses while a subprogram is executing.2.

Top of the Stack: It is the memory location in stack, where a word was most recently stored.

PUSHF (Push the Flag Register on the stack)PUSHFPUSHF instruction decrements the Stack Pointer (SP) register by two OR it pushes the current status of the Flag register tothe memory location(s) now pointed to by SP.

POP:POP DestinationPOP instruction copies the word from the top of the stack to the specified destination OR it increments the Stack Pointer(SP)register by two. Destination can be a register (or) a memory location that can be addressed by anyone of the 24 addressingmodes.

POPF(POP word from the top of the stack to the Flag register)POPFPOF instruction copies the word from the top of the stack to the Flag register and it increments the Stack Pointer(SP) register

by two.

XCHG:

XCHG Destination, SourceXCHG instruction interchanges the contents of the specified source and the specified destination. Source can be a register(or) a memory location that can be addressed by anyone of the 24 addressing modes. Destination can be a register (or) a

memory location that can be addressed by anyone of the 24 addressing modes.Note: 1. Both Source and Destination should not be two memory locations.XLAT/ XLATB (Translate a byte in AL)XLATBXLATB instruction translates a byte in AL from one code to another code. This instruction replaces the byte in AL with abyte pointed to by BX in a lookup table in memory. Before the XLATB instruction can be executed, the lookup table

containing the values for the new code must be put in memory. It copies the byte from the address pointed to by [BX]+[AL]back into AL.

LEA (Load Effective Address)

LEA Register, SourceLEA instruction determines the offset address of a variable or memory location named as source and puts this offset addressinto the specified register.

LES (Load Register OR ES with words from Memory)LES Register, Memory address of First Word)LES instruction copies a word from the two memory locations into the register specified in the instruction. It then copies the

word from next two memory locations into ES register.Note: 1.LES can be used to point DI and ES at the start of a string before a string instruction is to be executed.

LDS:LDS Register, Memory address of First Word)LDS instruction copies a word from the two memory locations into the register specified in the instruction. It then copies the

word from next two memory locations into DS register.Note: 1.LDS can be used to point SI and DS at the start of a string before a string instruction is to be executed.2. LDS BX,[4326] instruction copies the byte from the memory at a displacement 4326H in DS into BL, byte from 4327Hinto BH. Then it copies the content at a displacement of 4328H and 4329H in DS into DS register

3. Unlike all other instructions, LDS and LES instructions copies two words.


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Source can be an immediate number (or) a register (or) a memory location that can be addressed by anyone of the 24addressing modes. Destination can be a register (or) a memory location that can be addressed by anyone of the 24 addressing

modes. Both Source and Destination should not be two memory locations.

Note:1 .In all subtraction operations, Carry Flag acts like Borrow Flag.

SBB instruction subtracts the content of the specified source and the content of CF from the content of the specified

destination and result is put in the specified destination.

CMP (Compare Byte/Word)CMP Destination, Source

CMP instruction compares a byte/word from the specified source with a byte/word from the specified destination.Comparison is actually done internally using Subtraction, but result will not be stored in either of the operands. But basedon the result flags will be effected.In the example, CMP AX,BX

CF ZF SF[AX] > [BX] 0 0 0

[AX] = [BX] 0 1 0

[AX] < [BX] 1 0 1

NEG (Form 2s complement)NEG Destination

NEG instruction replaces the number in the specified destination with the 2s complement of that number. Destination can bea register (or) a memory location that can be addressed by anyone of the 24 addressing modes.

MUL (Multiplication of unsigned numbers)MUL SourceMUL instruction multiplies an unsigned byte from some source with an unsigned byte in AL register (or) an unsigned wordfrom some source with an unsigned word in AX. Source can be register (or) a memory location, which can be addressed by

any one of the 24-addressing modes.

-

When a byte is multiplied by the byte in AL, result is a word and is stored in AX.- When a word is multiplied by the word in AX, result is as long as 32-bits( double word) . The most significant

word of that double word is put in DX and least significant word of that double word is put in AX.

Note:1.

AF, PF, SF and ZF are undefined after MUL instruction.2.

If a byte is to be multiplied by the word, convert the byte to word and fill the upper byte of the word with all zeros.

IMUL (Multiplication of signed numbers)IMUL SourceIMUL instruction multiplies the signed byte from some source with the signed byte in AL register (or) signed word fromsome source with the signed word in AX. Source can be register (or) a memory location, which can be addressed by any oneof the 24-addressing modes.

-

When a signed byte is to be multiplied by the signed byte in AL, result is a signed word and it will be stored in AX.

- When a signed word is multiplied by the signed word in AX, result is as long as 32-bitsb(signed double word) . Themost significant word of that signed double word will be stored in DX and least significant word of that double wordwill be stored in AX.

Note:1.

AF, PF, SF and ZF are undefined after MUL instruction.2.

If a signed byte in AL is to be multiplied by signed word, convert the signed byte in AL to signed word by filling theAH register with the sign of the byte in AL.

CBW (Convert Signed Byte to Signed Word)CBW instruction converts the signed byte in AL to signed word OR it will be stored in AX. It copies the sign of the byte in

AL to all the bits of AH. AH is said to be the sign extension of AL. CBW affects no flags.

CWD (Convert Signed Word to Signed Double word)CWD instruction converts the signed word in AX to signed Double word and it will be stored in DX & AX. It copies the signof the byte in AX to all the bits of DX. In other words, it extends the sign of AX to all the bits of DX.


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DIV (Unsigned divide)DIV Source

DIV instruction is used to divide an unsigned word by a byte (or) to divide an unsigned DW by a word.

- When a word is divided by a byte, the word must be in AX register. Divisor can be in a register or a memory locationthat can be addressed by anyone of the 24 addressing modes. After division, AL contains an 8-bit result (quotient) & AH

will contain the 8-bit remainder.

- When a double word is divided by a word, the double word must be in DX and AX registers. Divisor can be in a registeror a memory location that can be addressed by anyone of the 24 addressing modes. After division, AX contains an 16-bit

result (quotient) & DX will contain the 16-bit remainder.

- If an attempt is made to divide by zero (or) if the quotient is too large to fit in AL, 8086 will automatically do Type-0interrupt.

Note:1. For DIV instruction, dividend(numerator) must be in AX (or) DX OR AX

IDIV (Divide by Signed byte/word)IDIV SourceIDIV instruction is used to divide a signed word by a signed byte (or) to divide an signed DW by a signed word.

- When a signed word is divided by a signed byte, the signed word must be in AX register. Divisor can be in a register or amemory location that can be addressed by anyone of the 24 addressing modes. After division, AL contains an 8-bit result(quotient) & AH will contain the 8-bit remainder.

-

When a signed double word is divided by a signed word, the signed double word must be in DX and AX registers.Divisor can be in a register or a memory location that can be addressed by anyone of the 24 addressing modes. After

division, AX contain an16-bit result (quotient) & DX will contain the 16-bit remainder.

- If an attempt is made to divide by zero (or) if the quotient is too large to fit in AL, 8086 will automatically do Type-0interrupt.

Note:1.

If we want to divide a signed byte by another signed byte, we must first put the dividend byte in AL and fill AH with

copies of the sign bit from AL.2.

If AL is +ve (sign bit=0), AH will be filled with all 0s.If AL is -ve (sign bit=1), AH will be filled with all 1s.

Logical Instructions:

AND (AND corresponding bits of the two operands)

AND Destination, SourceAND instruction ANDs the corresponding bits of specified source or specified destination. After execution, result will bestored in the specified destination.Source can be an immediate number (or) a register (or) a memory location that can be addressed by anyone of the 24addressing modes. Destination can be a register (or) a memory location that can be addressed by anyone of the 24 addressing


OR (OR corresponding bits of the two operands)OR Destination, SourceOR instruction ORs the corresponding bits of specified source or specified destination. After execution, result will be storedin the specified destination.Source can be an immediate number (or) a register (or) a memory location that can be addressed by anyone of the 24

addressing modes. Destination can be a register (or) a memory location that can be addressed by anyone of the 24 addressing


NOT (Invert each bit of the operands)NOT destinationNOT instruction inverts each bit (forms 1s complement) of the specified destination.

XOR (XOR corresponding bits of the two operands)XOR Destination, SourceXOR instruction XORs the corresponding bits of specified source or specified destination. After execution, result will be

stored in the specified destination.Source can be an immediate number (or) a register (or) a memory location that can be addressed by anyone of the 24addressing modes. Destination can be a register (or) a memory location that can be addressed by anyone of the 24 addressing


TEST ( AND corresponding bits of the operands to update flags)TEST Destination, SourceTEST instruction ANDs the corresponding bits of specified source or specified destination. After execution, result will not bestored in either of the operands, But based on the result flags will be effected.


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Source can be an immediate number (or) a register (or) a memory location that can be addressed by anyone of the 24addressing modes. Destination can be a register (or) a memory location that can be addressed by anyone of the 24 addressing


Note:1.TEST instruction is often used to set flags before a Conditional Jump instruction.

Shift Instructions:

SAL/SHL (Shift the bits of the operand left; Put zeros in LSB(s) )SAL Destination, Count

CF MSB LSB 0

SAL/SHL instruction shifts each bit in the specified destination some number of bit positions to the left. As a bit shifted outof LSB bit position, a 0 is put in LSB position.In case of multiple bit shifts, the desired number of shifts is loaded in CL register or CL is put in count position of theinstruction.

Note;1.

SAL/SHL instruction is used to multiply an unsigned binary number by a power of 2.

SAR (Shift the bits of the operand right; New MSB= Old MSB )

SAR Destination, Count

MSB MSB LSB CFSAR instruction shifts each bit in the specified destination some number of bit positions to the right. As a bit shifted out ofMSB bit position, a copy of old MSB is copied to the new MSB position.In case of multiple bit shifts, the desired number of shifts is loaded in CL register or CL is put in count position of theinstruction.

Note;1.

SAR instruction is used to divide a signed binary number by a power of 2.

SHR(Shift the bits of the operand right; Put Zero(s) in MSB(s))SHR Destination, Count

0 MSB LSB CFSHR instruction shifts each bit in the specified destination some number of bit positions to the right. As a bit shifted out of

MSB bit position, a 0 is put in LSB position.

In case of multiple bit shifts, the desired number of shifts is loaded in CL register or CL is put in count position of theinstruction.

Note;1.

SHR instruction is used to divide an unsigned binary number by a power of 2.

Rotate Instructions:

ROL (Rotate all bits of the operand left; MSB to LSB)ROL Destination, Count

CF MSB LSB

ROL instruction rotate all bits in the specified destination to the left some number of bit positions. The data bit rotated out of

MSB position is also copied into CF during ROL.In case of multiple bit rotates, the desired number of rotates is loaded in CL register or CL is put in count position of theinstruction.

ROR (Rotate all bits of the operand right; LSB to MSB)ROR Destination, CountROR instruction rotates all bits in the specified destination to the right some number of bit positions. The data bit rotated outof LSB position is also copied into CF during ROR.In case of multiple bit rotates, the desired number of rotates is loaded in CL register or CL is put in count position of the

instruction.

CF MSB LSB


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RCL (Rotate all bits of the operand left through Carry)RCL Destination, Count

CF MSB LSB

The middle letter of the mnemonic C indicate that CF is also in the loop. RCL instruction rotate all bits in the specified destination through Carry to the left some number of bit positions.In case of multiple bit rotates, the desired number of rotates is loaded in CL register or CL is put in count position of theinstruction.

RCR (Rotate all bits of the operand right through Carry)RCR Destination, CountRCR instruction rotates all bits in the specified destination through Carry to the right some number of bit positions.

In case of multiple bit rotates, the desired number of rotates is loaded in CL register or CL is put in count position of theinstruction.

CF MSB LSB

Note:

1.

Rotate instructions effect only CF & OF.

- If MSB is changedby a single bit rotate, OF will be 1

- CF will contain the last most recently rotated out of the MSB/LSB.

String Instructions:MOVS/MOVSB/MOVSW


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IV (c) BCD Arithmetic:

The microprocessor allows manipulation of BCD OR ASCII dataBCD used in Cash registers OR ASCII used by many programs

There are two instructions

DAA decimal adjust after additionDAS decimal adjust after subtraction

Both instructions correct the result. The BCD number is stored as packed form 2 digits/byte OR if unpacked form means 1digit/byte it functions with AL only.DAA decimal adjust after additionThe result is in AL

The Logic of this instruction

If lower nibble>9 or AF=1 add 06After adding 06 if upper nibble>9 or CF=1 add 60

DAA instruction follows ADD or ADCExample1

ADD AL,CL

DAA

Let AL=53 OR CL=29AL=53+29AL=7CAL=7C+06 (as C>9)AL=82

Example 2

Let AL=73 CL=29AL=9CAL=9C+06 (as C>9)AL=A2

AL=A2+60=02 OR CF=1

The instruction affects AF,CF,PF OR ZFExample3

MOV DX,1234HMOV BX,3099HMOV AL,BL

ADD AL,DLDAA

MOV AL,BH

ADC AL,DHDAAMOV CH,AL

BL=99H DL=34H99+34=CDAL=CD+6(D>9)

AL=D3AL=D3+60(D>9)AL=33 OR CF=1

BH=30 DH=12AL=30+12+CFAL=43DAA does not do anythingThe result is placed in CX=4333

DAS instruction follows subtractionThe result is in ALLogic of this instruction

If lower nibble>9 or AF=1 subtract 06


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Data size bit (W) defines whether the operation to be performed is an 8 bit or 16 bit data

W=0 indicates 8 bit operationW=1 indicates 16 bit operation

The second byte of the instruction usually identifies whether one of the operORs is in memory or whether both are registers.

This byte contains 3 fields. These are the mode (MOD) field, the register (REG) field OR the Register/Memory (R/M) field.

MOD (2 bits) Interpretation

00 Memory mode with no displacement follows except for 16 bit displacement when

R/M=110

01 Memory mode with 8 bit displacement

10 Memory mode with 16 bit displacement

11 Register mode (no displacement)

Register field occupies 3 bits. It defines the register for the first operOR which is specified as source or destination by the Dbit.

REG W=0 W=1

000 AL AX

001 CL CX

010 DL DX

011 BL BX

100 AH SP

101 CH BP

110 DH SI

111 BH DI

The R/M field occupies 3 bits. The R/M field along with the MOD field defines the second operOR as shown below.

MOD 11

R/M W=0 W=1

000 AL AX

001 CL CX

010 DL DX

011 BL BX

100 AH SP

101 CH BP

110 DH SI

111 BH DI

Ef fective Address Calculation

R/M MOD=00 MOD 01 MOD 10

000 (BX) + (SI) (BX)+(SI)+D8 (BX)+(SI)+D16

001 (BX)+(DI) (BX)+(DI)+D8 (BX)+(DI)+D16

010 (BP)+(SI) (BP)+(SI)+D8 (BP)+(SI)+D16

011 (BP)+(DI) (BP)+(DI)+D8 (BP)+(DI)+D10

100 (SI) (SI) + D8 (SI) + D16

101 (DI) (DI) + D8 (DI) + D16

110 Direct address (BP) + D8 (BP) + D16

111 (BX) (BX) + D8 (BX) + D16

In the above, encoding of the R/M field depends on how the mode field is set. If MOD=11 (register to register mode), thisR/M identifies the second register operOR.


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MOD selects memory mode, then R/M indicates how the effective address of the memory operOR is to be calculated. Bytes3 through 6 of an instruction are optional fields that normally contain the displacement value of a memory operOR OR / or

the actual value of an immediate constant operOR.

Example 1 : MOV CH, BLThis instruction transfers 8 bit content of BL

I nto CH

The 6 bit Opcode for this instruction is 1000102D bit indicates whether the register specified by the REG field of byte 2 is a

source or destination operOR.D=0 indicates BL is a source operOR.W=0 byte operation

In byte 2, since the second operOR is a register MOD field is 11 2.The R/M field = 101 (CH)

Register (REG) field = 011 (BL)

Hence the machine code for MOV CH, BL is10001000 11 011 101Byte 1 Byte2

= 88DD16

Example 2 : SUB Bx, (DI)This instruction subtracts the 16 bit content of memory location addressed by DI OR DS from Bx. The 6 bit Opcode for SUBis 0010102.

D=1 so that REG field of byte 2 is the destination operOR. W=1 indicates 16 bit operation.MOD = 00REG = 011R/M = 101The machine code is 0010 1011 0001 1101

2 B 1 D

2B1D16

Summary of all Addressing Modes

Example 3 : Code for MOV 1234 (BP), DX

Here we have specify DX using REG field, the D bit must be 0, indicating the DX is the source register. The REG field mustbe 010 to indicate DX register. The W bit must be 1 to indicate it is a word operation. 1234 [BP] is specified using MOD

value of 10 OR R/M value of 110 OR a displacement of 1234H. The 4 byte code for this instruction would be 89 96 34 12H.

Opcode D W MOD REG R/M LB displacement HB displacement

100010 0 1 10 010 110 34H 12H

Example 4 : Code for MOV DS : 2345 [BP], DX

Here we have to specify DX using REG field. The D bit must be o, indicating that Dx is the source register. The REG fieldmust be 010 to indicate DX register. The w bit must be 1 to indicate it is a word operation. 2345 [BP] is specified with

MOD=10 OR R/M = 110 OR displacement = 2345 H.

MOD / R/M Memory Mode (EA Calculation) Register Mode

00 01 10 W=0 W=1

000 (BX)+(SI) (BX)+(SI)+d8 (BX)+(SI)+d16 AL AX

001 (BX) + (DI) (BX)+(DI)+d8 (BX)+(DI)+d16 CL CX

010 (BP)+(SI) (BP)+(SI)+d8 (BP)+(SI)+d16 DL DX

011 (BP)+(DI) (BP)+(DI)+d8 (BP)+(DI)+d16 BL BX

100 (SI) (SI) + d8 (SI) + d16 AH SP

101 (DI) (DI) + d8 (DI) + d16 CH BP

110 d16 (BP) + d8 (BP) + d16 DH SI

111 (BX) (BX) + d8 (BX) + d16 BH DI


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Whenever BP is used to generate the Effective Address (EA), the default segment would be SS. In this example, we want thesegment register to be DS, we have to provide the segment override prefix byte (SOP byte) to start with. The SOP byte is

001 SR 110, where SR value is provided as per table shown below.

SR Segment register

00 ES

01 CS

10 SS

11 DS

To specify DS register, the SOP byte would be 001 11 110 = 3E H. Thus the 5 byte code for this instruction would be 3E 8996 45 23 H.

SOP Opcode D W MOD REG R/M LB disp. HD disp.

3EH 1000 10 0 1 10 010 110 45 23

Suppose we want to code MOV SS : 2345 (BP), DX. This generates only a 4 byte code, without SOP byte, as SS is already

the default segment register in this case.

Example 5 :Give the instruction template OR generate code for the instruction ADD OFABE [BX], [DI], DX (code for ADD instructionis 000000)

ADD OFABE [BX] [DI], DXHere we have to specify DX using REG field. The bit D is 0, indicating that DX is the source register. The REG field must

be 010 to indicate DX register. The w must be 1 to indicate it is a word operation. FABE (BX + DI) is specified using MODvalue of 10 OR R/M value of 001 (from the summary table). The 4 byte code for this instruction would be

Opcode D W MOD REG R/M 16 bit disp. =01 91 BE FAH000000 0 1 10 010 001 BEH FAH

Example 6 :

Give the instruction template OR generate the code for the instruction MOV AX, [BX](Code for MOV instruction is 100010)

AX destination register with D=1 OR code for AX is 000 [BX] is specified using 00 Mode OR R/M value 111It is a word operation

Opcode D W Mod REG R/M=8B 07H

100010 1 1 00 000 111

Segment Over Ride Prefix

SOP is used when a particular offset register is not used with its default base segment register, but with a different base

register. This is a byte put before the OPCODE byte.

0 0 1 S R 1 1 0

SR Segment Register

00 ES

01 CS

10 SS

11 DS

Here SR is the new base register. To use DS as the new register 3EH should be prefix.

OperOR Register Default With over ride prefix


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IP (Code address) CS Never

SP(Stack address) SS Never

BP(Stack Address) SS BP+DS or ES or CS

SI or DI(not including Strings) DS ES, SS or CS

SI (Implicit source Address for

strings)

DS

DI (Implicit Destination Address for

strings)

ES Never

Examples: MOV AX, DS: [BP], LODS ES: DATA1

S4 S3 Indications

0 0 Alternate data

0 1 Stack

1 0 Code or none

1 1 Data

Bus High Enable / Status

BHE A0 Indications

0 0 Whole word

0 1 Upper byte from or to odd address

1 0 Lower byte from or to even address

1 1 none

Assembler Directives:

Assembler converts Assembly Language Program into Machine UnderstORable

Language. For doing this conversion, the directions given to the assembler are known as

Assembler Directives.

Assembler directives are classified into

I) Data definition OR Storage allocation directives:

DB, DW, DD, DQ, DT, STRUCT, RECORD

II) Program Organization directives:

SEGMENT, ENDS, ASSUME, GROUP

III)

Alignment directives:

EVEN, ORG

IV)Program End directive:

END

V) Value returning attribute directives:

LENGTH, SIZE, OFFSET, SEG,TYPE

VI)Procedure definition directives:

PROC, ENDP

VII)Macro definition directives:

EQU, MACRO, ENDM


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Memory is reserved for use in the future by using a ? as an operOR for DB DW or DD directive. The assembler sets

aside a location OR does not initialize it to any specific value (usually stores a zero). The DUP (duplicate) directivecreates an array OR stores a zero.

ExampleData1 DB 5 DUP(?)This reserves 5 bytes of memory for a array data1 OR initializes each location with 05H

ALIGN: memory array is stored in word boundaries.

ExampleALIGN 2 means storing from an even address

Address 0 XX

Address 1 YY

Address 2 XX

The data XX is aligned to the even address.

ASSUME, EQU, ORG

ASSUME tells the assembler what names have been chosen for Code, Data Extra OR Stack segments. Informs theassembler that the register CS is to be initialized with the address allotted by the loader to the label CODE OR DS is

similarly initialized with the address of label DATA.

ExampleASSUME CS: Name of code segmentASSUME DS: Name of the data segment

ASSUME CS: Code1, DS: Data1

EQU: Equates a numeric, ASCII(American StORard Code for Information Interchange) or label to another label.

ExampleData SEGMENT

Num1 EQU 50HNum2 EQU 66H

Data ENDS

Numeric value 50H OR 66H are assigned to Num1 OR Num2

ORG: Changes the starting offset address of the data in the data segment

ExampleORG 100H

100 data1 DB 10Hit can be used for code too.

PROC & ENDP: indicate the start OR end of the procedure. They require a label to indicate the name of the procedure.

NEAR: the procedure resides in the same code segment. (Local)

FAR: resides at any location in the memory.

ExampleAdd PROC NEAR

ADD AX,BX

MOV CX,AXRET

Add ENDP

PROC directive stores the contents of the register in the stack.

EXTRN, PUBLIC informs the assembler that the names of procedures OR labels declared after this directive have beenalready defined in some other assembly language modules.

ExampleIf you want to call a Factorial procedure of Module1 from Module2 it must be declared asPUBLIC in Module1.

Example

A sample for full segment definition

Data SEGMENT

Num1 DB 10HNum2 DB 20HNum3 EQU 30H


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Data ENDS

ASSUME CS:Code,DS:DataCode SEGMENT

START: MOV AX,DataMOV DS,AX

MOV AX,Num1MOV CX,Num2

ADD AX,CXCode ENDS

Example

A sample for small model

. MODEL SMALL

.DataNum1 DB 10HNum2 DB 20H

Num3 EQU 30H

.CodeHERE: MOV AX,@Data

MOV DS,AXMOV AX,Num1

MOV CX,Num2ADD AX,CX

Assembly Language Program Development Tools:

For all assembly language programs , you will probably want to use some type of microcomputer developmentsystem(MDS) OR program development tools to make your work easier.Editor

An editor is a program which allows you to create a file containing the assembly language statements for yourprogram. Examples of suitable editors are PC Write, Word star, OR the editor that comes with some assemblers.

As we type in your program, the editor stores the ASCII codes for the letters OR numbers in successive RAMlocations. If we make a typing error, the editor will let you back up OR correct it. If you leave out a program statement, the

editor will let you move everything down OR insert the line. This is much easier than working with pencil OR paper, even ifwe type as slowly as I do.Assembler

An assembler program is used to translate the assembly language mnemonics for instructions to the correspondingbinary codes

The assembler generates two files on the floppy or hard disk. The first file, called the object file is given theextension. OBJ. The object file contains the binary codes for the instructions. The second file generated by the assembler iscalled the assembler list file OR is given the extension.

A linker or locator will be used to assign the physical starting addresses for the segments

LinkerA Linker is a program used to join several object files into one large object file. When writing large programs, it is

usually much more efficient to divide the large program into smaller modules. Each module can be individually written,tested, OR debugged. Then when all modules work their object modules can be linked together to form a large, functioning

program.The linker produces a link file which contains the binary codes for all the combined modules. The linker also

produces a link map file which contains the address information about the linked files. The linker, however does not assign

absolutes addresses to the program. The linkers which come with the TASM or MASM assemblers produce link with the.EXE extension.

LocatorA locator is a program used to assign the specific addresses of the segments of object code are to be loaded into the

memory.Debugger


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A debugger is a program which allows you to load your object code program into system debug it. The debuggerallows you to look at the contents of registers OR memory locations after your program runs. It allows you to change the

contents of some debuggers allow you to stop execution after each instruction so that you can check or alter memory ORregister contents. A debugger also allows you to set a break point at any point in your program. If you insert a breakpoint, thedebugger will run the program up to the instruction where you put the breakpoint OR then stop execution. You can thenexamine register OR memory contents to see whether the results are correct, you can move the break point to a later point in

the program. If the results are not correct ,you can check the program up to that point to find out why they are not correct.

EmulatorAn emulator is a mixture of hardware OR software. It is usually used to test OR debug the hardware of an external

system, such as the prototype of a microprocessor-based instrument. Part of the hardware of an emulator is a multi wire cablewhich connects the host system in place of its microprocessor. Through this connection the software of the emulator allows

you to download your object code program into RAM in the system being tested OR run it. Like a debugger , an emulatorallows you to load OR run programs, examine OR change the contents of memory locations, OR insert breakpoints in theprogram. The emulator stores this trace data, as it is called, in a large RAM.

Another powerful feature of an emulator is the ability to use either system memory or the memory on the prototype

for the program you are debugging.


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Pin Diagram of 8086:

8086

AD15Vcc40

39

38 A16/S3

A17/S437

36 A18/S5

A19/S635BHE/S734

MN/MX

RD

RG GT0/ (HOLD)

RQ GT1/ (HLDA)LOCK WR( )

S2 I0(M/ )

S1 R(DT/ )

S0 DEN( )

QS0 (ALE)

QS1 ( )INTATEST

READY

RESET

33

32

31

30

29

28

27

26

25

24

23

22

2120

19

18

17

16

15

14

13

12

11

10

9

8

76

5

4

3

2

1GND

AD14

AD13

AD12

AD11

AD10AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

NMIINTR

CLK

GND

Classification OR Description of Pins of 8086:

8086 is a 40 pin DIP using MOS technology. It has 2 GNDs as circuit complexity demORs a large amount of current

flowing through the circuits, OR multiple grounds help in dissipating the accumulated heat etc. 8086 works on two modes ofoperation namely, Maximum Mode OR Minimum Mode.

(i) Power Connections

GNDPin no. 1, 20

Ground

VCCPin no. 40

VCC: +5V power supply pin

CLKPin no. 19Type I

Clock: provides the basic timing for the processor OR bus controller. It is asymmetric with a 33% duty cycle to provide

optimized internal timing.


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INTR (I): Interrupt Request

It is a level triggered input which is sampled during the last clock cycle of each instruction to determine if theprocessor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector look uptable located in system memory. It can be internally masked by software resetting the interrupt enable bit

INTR is internally synchronized. This signal is active HIGH.

(ii) Address/ Data Lines

Pin Description

AD15-AD0Pin no. 2-16, 39Type I/O

Address Data bus:These lines constitute the time multiplexed memory/ IO address (T1) OR data (T2, T3, TW, T4) bus. A0is

analogous to BHE for the lower byte of of the data bus, pins D7-D0. It iss low when a byte is to be transferred on the lower

portion of the bus in memory or I/O operations. Eightbit oriented devices tied to the lower half would normally use A0to

condition chip select functions. These lines are active HIGH OR float to 3-state OFF during interrupt acknowledge OR local

bus hold acknowledge.

(iii) Address Lines


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AD0 - AD15 (I/O): Address Data Bus

These lines constitute the time multiplexed memory/IO address during the first clock cycle (T1) OR data during T2, T3

OR T4 clock cycles. A0 is analogous to BHE for the lower byte of the data bus, pins D0-D7. A0 bit is Low during T1 statewhen a byte is to be transferred on the lower portion of the bus in memory or I/O operations. 8-bit oriented devices tied to the

lower half would normally use A0 to condition chip select functions. These lines are active high OR float to tri-state during

interrupt acknowledge OR local bus "Hold acknowledge". Fig. 2 shows the timing of AD0AD15 lines to access data ORaddress.

AD0 - AD15 Address Data

T4 T1 T2 T3 T4

Fig. .2

A19/S6, A18/S5, A17/S4, A16/S3Pin no. 35-38Type O

Address / Status: During T1 these are the four most significant address lines for memory operations. During I/O operations

these lines are low. During memory OR I/O operations, status information is available on these lines during T 2, T3, TWOR

T4. The status of the interrupt enable FLAG bit (S5) is updated at the beginning of each CLK cycle. A 17/S4OR A16/S3are

encoded as shown.

A17/S4 A16/S3 Characteristics

0 (LOW) 0 Alternate Data

0 1 Stack

1(HIGH) 0 Code or None

1 1 Data

S6is 0 (LOW)

This information indicates which relocation register is presently being used for data accessing.

These lines float to 3-state OFF during local bus hold acknowledge.

A19/S6, A18/S5, A17/S4, A16/S3 (0): Address/Status

During T1 state these lines are the four most significant address lines for memory operations. During I/O operations

these lines are low. During memory OR I/O operations, status information is available on these lines during T2, T3, OR

T4 states.

S5:The status of the interrupt enable flag bit is updated at the beginning of each cycle. The status of the flag is

indicated through this bus.S6:When Low, it indicates that 8086 is in control of the bus. During a "Hold acknowledge" clock period, the 8086

tri-states the S6 pin OR thus allows another bus master to take control of the status bus.

S3 & S4:Lines are decoded as follows:

Table 1

After the first clock cycle of an instruction execution, the A17/S4 OR A16/S3 pins specify which segment registergenerates the segment portion of the 8086 address. Thus by decoding these lines OR using the decoder outputs as chip selects

A17/S4 A16/S3 Function

0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access


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for memory chips, up to 4 Megabytes (one Mega per segment) of memory can be accesses. This feature also provides adegree of protection by preventing write operations to one segment from erroneously overlapping into another segment OR

destroying information in that segment.

S4 S3 Indications

0 0 Alternate data

0 1 Stack

1 0 Code or none

1 1 Data

----- Value of Interrupt Enable flag

----- Always low (logical) indicating 8086 is on the bus. If it is tristated another

bus master has taken control of the system bus.

----- Used by 8087 numeric coprocessor to determine whether the CPU is a 8086

or 8088

BHE /S7 (O): Bus High Enable/Status

During T1 state theBHE should be used to enable data onto the most significant half of the data bus, pins D15 -

D8. Eight-bit oriented devices tied to the upper half of the bus would normally use BHE to control chip select functions.

BHE is Low during T1 state of read, write OR interrupt acknowledge cycles when a byte is to be transferred on the highportion of the bus.

The S7 status information is available during T2, T3 OR T4 states. The signal is active Low OR floats to 3-stateduring "hold" state. This pin is Low during T1 state for the first interrupt acknowledge cycle.

7/SBHE - Pin No. 34Type O

Bus High Enable / Status: During T1 the Bus High Enable signal (BHE )should be used to enable data onto the most

significant half of the data bus, pins D15-D8. Eight bit oriented devices tied to the upper half of the bus would normally use

BHE to condition chip select functions. BHE is LOW during T1 for read, write, OR interrupt acknowledge cycles when a

byte is to be transferred on the high portion of the bus. The S,7status information is available during T2, T3OR T4. The signal

is active LOW OR floats to 3-state OFF in hold. It is LOW during T1for the first interrupt acknowledge cycle.

BHE A0 Characteristics

0 0 Whole word

0 1 Upper byte from / to odd address

1 0 Lower byte from / to even address

1 1 None

MXMN/ - Pin no. 33Type - I

Minimum / Maximum: indicates what mode the processor is to operate in.

If the local bus is idle when the request is made the two possible events will follow:

1. Local bus will be released during the next clock.

5S

6S

7S


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2.

A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply with

condition number 1 already satisfied.

MN/MX (I): Maximum / Mi nimum

This pin indicates what mode the processor is to operate in. In minimum mode, the 8086 itself generates all bus

control signals. In maximum mode the three statussignals are to be decoded to generate all the bus control signals.

RD - Pin no. 32, Type O

Read: Read strobe indicates that the processor is performing a memory of I/O read cycle, depending on the state of the S2pin.

This signal is used to read devices which reside on the 8086 local bus. RD is active LOW during T2, T3OR TWof any read

cycle, OR is guaranteed to remain HIGH in T2until the 8086 local bus has floated.

This signal floats to 3-state OFF in hold acknowledge.

RD (O): READ

The Read strobe indicates that the processor is performing a memory or I/O read cycle. This signal is active low during T2

OR T3 states OR the Tw states of any read cycle.This signal floats to tri-state in "hold acknowledge cycle".

RESETPin no. 21Type I

Reset: causes the processor to immediately terminate its present activity. The signal must be active HIGH for at least four

clock cycles. It restarts execution, as described in the instruction set description, when RESET returns LOW. RESET is

internally synchronized.

Reset (I)

Reset causes the processor to immediately terminate its present activity. To be recognised, the signal must be activehigh for at least four clock cycles, except after power-on which requires a 50 Micro Sec. pulse. It causes the 8086 to

initialize registers DS, SS, ES, IP OR flags to all zeros. It also initializes CS to FFFF H. Upon removal of the RESET signalfrom the RESET pin, the 8086 will fetch its next instruction from the 20 bit physical address FFFF0H. The reset signal to8086 can be generated by the 8284. (Clock generation chip). To guarantee reset from power-up, the reset input must remainbelow 1.5 volts for 50 Micro sec. after Vcc has reached the minimum supply voltage of 4.5V. The RES input of the 8284 canbe driven by a simple RC circuit as shown in fig.3.

+5VR

Normal

Reset Key

RES

F/C

X1

X2 CLKCLK

RESET RESET

SYSTEM RESET

8086 p

C

8284

Fig. .3

The value of R OR C can be selected as follows:

Vc (t) = V (1 - e-t /RC

) t = 50 Micro sec.V = 4.5 volts, Vc = 1.05V OR RC = 188 Micro sec.C = 0.1 Micro F; R = 1.88 K ohms.

CPU component Contents

Flags Cleared

Instruction Pointer 0000H

mpmc notes

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