chapter 8 -- analysis and synthesis of synchronous sequential circuits
DESCRIPTION
Chapter 8 -- Analysis and Synthesis of Synchronous Sequential Circuits. The Synchronous Sequential Circuit Model. Figure 8.1. Mealy Machine Model. Figure 8.2. Mealy Machine Timing Diagram -- Example 8.1. Figure 8.3. Moore Machine Model. Figure 8.4. - PowerPoint PPT PresentationTRANSCRIPT
Chapter 8 -- Analysis and Synthesis ofSynchronous Sequential Circuits
The Synchronous Sequential Circuit Model
z m
z 1
y r
C lo ck
y 1
M em o ry
C o m b in a tio n a llo g ic
... ...
. .....
x n
x 1
Y r Y 1
Figure 8.1
Mealy Machine Model
C /0A /1C /0
0 /0
1 /1
1 /0
1 /0
0 /10 /0
(a )
(b )
X /Z
P resen tsta te
In p u t x0 1
N ex t sta te/o u tp u t
B /1B /0A /0
ABC
A
B C
Figure 8.2
Mealy Machine Timing Diagram -- Example 8.1
C lo c k
S ta te
In p u t x
O u tp u t z
0 1
A C
T 0 T 1 T 2 T 3 T 4 T 5
A B C AA
1 0 1 0
01 01 0 0
Figure 8.3
Moore Machine Model
XYW
(a )
(b )
P resen tsta te
In p u t x0 1YXX
WXY
O u tp u ts010
W /0 X /1
Y /0
01
10 0
1
Figure 8.4
Moore Machine Timing Diagram -- Example 8.2
C lock
S ta te
In p u t x
O u tp u t z
0 1
X Y
T 0 T 1 T 2 T 3 T 4 T 5
W Y X XW
1 0 1 0
00 10 1 0
Figure 8.5
Analysis of Sequential Circuit State Diagrams -- Example 8.3
0 /0 1 /0
0 /0
1 /1
0 0 0 1 11
x /z
0 /01 /0
Figure 8.6
Timing Diagram for Example 8.3
C lo ck
x
y 1
y 2
z
0 10 1 1 10 1 0 0
0 00 0 0 10 1 1 0
0 00 1 1 11 1 1 0
0 00 0 0 10 1 0 0
Figure 8.7
Analysis of Sequential Circuit Logic Diagrams
(a )
(b )
C o m b in a tio n a l lo g ic
M em o ry
C lo ck
D
C
Q
Q
D
C
Q
Q
0 1 2 3 4
D t
t/D t
y
y
Y
x
z
Figure 8.8
Timing Diagram for Figure 8.8 (a)
C lo ck
G litch
x
y
z
Y = D
0
t/D t0 1 2 3 4 5 6 7 8
0
0
0
1
0
1
0
1
1
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Figure 8.9
State Table and State Diagram for Figure 8.8 (a)
A /0
0 1
A
B
B /0
B /0 A /1
P resen tsta te
x kIn p u t
(c)N ex t sta te/o u tp u t
0 /0
A B1 /0
1 /1
0 /0
(d )
0 /0
0 1
1 /0
1 /0 0 /1
P resen tsta te
y k
x kIn p u t
(b )N ex t sta te/o u tp u t
0 1
0
1
P resen tsta te
y k
x kIn p u t
(a )
x /z
0
1
Figure 8.10
K-Maps for Circuit of Figure 8.8 (a)
0 1
A
B
P resen tsta te
x kIn p u t
(c)(b )
0 1
0
1
y k
x k
(a )
0
1
1
0
0 1
0
1
y k
x k
0
0
0
1
y k + 1 /z k
A /0 B /0
B /0 A /1
Figure 8.11
Synchronous Sequential Circuit with T Flip-Flop -- Example 8.4
xz
Q
C lo cky
y
CQ
T
Figure 8.12
Timing Diagram for Example 8.4
1 01 0 01
C lo ck
0x
y
z
T
0
1 00 0 110 1
1 00 0 010 0
2 43 6 851 70
Figure 8.13
State Table and State Diagram for Example 8.4
(a )
1 /0
y k + 1 /zk
x /z
0 /01 /1
y k
x k
y k
x k
y k + 1 /zk
(b )
P resen tsta te
x k
N ex t sta te/o u tp u t
(c)
0 /0
(d )
A B
0 1
A
B
B /0
B /0
A /0
A /1
0 10
1
1 /0
1 /0
0 /0
0 /1
0 1
1
0
Figure 8.14
K-Maps for Example 8.4
(a )
zk
x k
0 1
0
1
(b ) (c)
0
0
0
1
y k
T k
x k
0 1
0
1
1
0
0
1
y k
y k + 1
x k
0 1
0
1
1 *
1
0
0 *
y k
(d )
y k + 1 /zk
x k
0 1
0
1
1 /0
1 /0
0 /0
0 /1
y k
Figure 8.15
Synchronous Sequential Circuit with JK Flip-flops -- Example 8.5
C lo ck
x
z
y 1
y 1
y 2
y 2
C
J 1
K 1
Q
Q
Q
Q
C
J 2
K 2
Figure 8.16
Timing Diagram and State Table for Example 8.5
C
x 0
y 1
y 2
J 1 = x y 2
K 1 = x
J 2 = x
K 2 = x + y 1
z = x y 1 y 2
0 1 1 1 1 0 0
1 0 0 0 1 1 1 0
0 0 0 1 0 1 1 0
0 0 0 0 0 1 0 0
0 0 /0
0 0 /0
0 0 /0
0 0 /0
0 1 /0
1 0 /0
11 /1
11 /0
y 1 y 2
x0 1
0 0
0 1
11
1 0
(b )
(a )
Figure 8.17
K-Maps for Example 8.5
y 1 y 2
x
0
0 1
0 0
0 1
11
1 0
0
0 1
0 1
0 0
J 1
x
1
0 1
0 0
0 1
11
1 0
0
1 0
1 0
1 0
K 1
x
0
0 1
0 0
0 1
11
1 0
1
0 1
0 1
0 1
J 2
x
1
0 1
0 0
0 1
11
1 0
1
1 1
1 0
1 0
K 2
x
0
0 1
0 0
0 1
11
1 0
0
0 0
0 1
0 0
z
y 1 y 2
y 1 y 2 y 1 y 2 y 1 y 2
Figure 8.18
Generating the State Table From K-maps -- Example 8.5
x
0 0 11
1 0 11
1 0 1 0
0 0 1 0
Y 1 Y 2 Y 1 Y 2 /z
y 1 y 2
0 1
0 1
0 0
0 1
11
1 0
0 1
0 1 0 1
0 1 0 1
0 1 0 1
(a )
J 1 K 1 J 2 K 2 J 1 K 1 J 2 K 2
(b ) (c )
0 1x
0 0
0 1
11
1 0
0 0
0 0
0 0
0 0
0 1
1 0
11
11
0 1x
0 0
0 1
11
1 0
0 0 /0
0 0 /0
0 0 /0
0 0 /0
0 1 /0
1 0 /0
11 /1
11 /0
y 1 y 2 y 1 y 2
Figure 8.19
Synchronous Sequential Circuit Synthesis
(a ) C om p le te ly sp ec if ied c ircu it
(b ) In com p le te ly sp ec if ied c ircu it
1 /1
1 /0
1 /01 /0
0 /0
0 /0
0 /- 0 /0
0 /0
0 /0
1 /1
0 /-1 /-
1 /1
A B
C
D
AB
C
0 1x
A
B
C
D
D /0
D /0
D /0
D /0
B /0
C /0
B /0
A /1
0 1x
A
B
C
B /-
B /0
A /-
- /1
C /1
A /-
Figure 8.20
Introductory Synthesis Example -- Example 8.6
(a ) S ta te ta b le
S ta te y 1
0
1
1
0
x
0
0 1
0 0
0 1
11
1 0
0
0 1
0 0
1 0
0
0
1
1
y 2
A
B
C
D
Y 1 Y 2/z
(d ) O u tp u t K -m a p
x
0
0 1
0 0
0 1
11
1 0
0
0 1
0 1
1 1
x
0
0 1
0 0
0 1
11
1 0
1
0 1
1 0
1 0
(b ) S ta tea ss ig n m en t
D 1 (= Y 1 )
(c )T ra n s it ionta b le
D 2 (= Y 2 )(e ) E x c ita t ion K -m a p s (f) L og ic d ia g ra m
x
z
C lock
y 1
y 1
y2
y2
z
Q
Q C
D 1
Q
Q C
D 2
0 1x
A
B
C
D
A /0
A /0
B /0
C /1
B /0
C /1
D /0
D /0
0 1x
0 0
0 1
11
1 0
0 0 /0
0 0 /0
0 1 /0
11 /1
0 1 /0
11 /1
1 0 /0
1 0 /0
y 1 y 2
y 1 y 2 y 1 y 2y 1 y 2
Figure 8.21
Flip-flop Input Tables -- Example 8.6
S ta tetra n s it ion sQ (t) Q (t + e )
(a ) D f lip -f lop
0
0
1
1
0
1
0
1
R eq u iredin p u ts
D (t)
0
1
0
1
S ta tetra n s it ion sQ (t) Q (t + e )
(b ) C locked S R
0
0
1
1
0
1
0
1
R eq u iredin p u ts
S (t) R (t)
0
1
0
d
d
0
1
0
S ta tetra n s it ion sQ (t) Q (t + e )
(c ) C locked T f lip -f lop
0
0
1
1
0
1
0
1
R eq u iredin p u ts
T (t)
0
1
1
0
S ta tetra n s it ion sQ (t) Q (t + e )
(d ) C locked J K f lip -f lop
0
0
1
1
0
1
0
1
R eq u iredin p u ts
J (t) K (t)
0
1
d
d
d
d
1
0
Figure 8.22
Generating the JK Flip-flop Excitation Maps --Example 8.7
x
0
0 1
0 0
0 1
11
1 0
0
0
d
d d
(c ) E x c ita t ion m a p s
x
d
0 1
0 0
0 1
11
1 0
d
d d
1 0
0 0
x
0
0 1
0 0
0 1
11
1 0
1
d d
d d
1 0
K 1 J 2
1
d
x
d
0 1
0 0
0 1
11
1 0
d
1
d
0 1
d
K 2
0
J 1
(b ) E x c ita t ion ta b le
J 1 K 1 J 2 K 2Y 1 Y 2/z
0 1x
0 0
0 1
11
1 0
0 d
0 d
d 1
d 0
0 d
1 d
d 0
d 0
(a ) T ra n s it ion ta b le
y 1 y 2 0 1x
0 0
0 1
11
1 0
0 0 /0
0 0 /0
0 1 /0
11 /1
0 1 /0
11 /1
1 0 /0
1 0 /0
0 1x
0 0
0 1
11
1 0
0 d
d 1
d 0
1 d
1 d
d 0
d 1
0 d
y 1 y 2 y 1 y 2
y 1 y 2y 1 y 2 y 1 y 2y 1 y 2
Figure 8.23
Clocked JK Flip-Flop Implementation --Example 8.7
x
z
C lock
y 1
y 2
Q
Q
C
J 1
Q
Q
C
J 2
K 1
K 2
y 2
y 1
Figure 8.24
Application Equation Method for Deriving Excitation Equations -- Example 8.8
y 1 y 2
x
0
0 1
0 0
0 1
11
1 0
0
0 1
0 1
1 1
Y 1
y 1
x
0
0 1
0 0
0 1
11
1 0
1
0 1
1 0
1 0
Y 2
y 2
y 1 y 2
Figure 8.25
Sequence Recognizer for 01 Sequence -- Example 8.9
1 /1
1 /0 0 /0
(d)
A B0 /01 /0 0 /0
(c )
A B0 /0
1 /0
(b)
A B0 /01 /0
(a )
A
Figure 8.26
Synthesis of the 01 Recognizer with SR Flip-flops
(b ) T ransition tab le and output m ap
C lock
y k + 1
x
y k
1
0 1
0
1
0
1 0
x
z
y k
0
0 1
0
1
0
0 1
x
B /0
0 1
A
B
A /0
B /0 A /1
x
(a ) S ta te tab le
(c ) E xcita tion m apsS
y k
1
0 1
0
1
0
d 0
x
R
y k
0
0 1
0
1
d
0 1
x
z(d ) L og ic d iagram
1 0 1 0 1
y
x
z
C lock
S = xR = x
00 0 10 10 0 0 01 01 1 1 11100
10
1
(e ) T im ing d iagram
S
R
Q
C
y k
Q
Figure 8.27
Realization of 01 Recognizer with T Flip-flops
(a ) C locked T f lip -flopex c ita t ion m a p
T
x0 1
0
1
1
0
0
1
y k
(c ) C locked J K ex c ita t ion m a p s
J
x0 1
0
1
1
d
0
d
y k
K
x0 1
0
1
d
0
d
1
y k
T
xyQ
C
C lock
Q
(b ) C locked T f lip -f lopim p lem en ta tion
Figure 8.28
Design of a Recognizer for the Sequence 1111 --Example 8.11
(a ) S ta te d iagram
0/0 0 /00 /0
1 /01 /0 1 /0
1 /1
0 /0
y 1ky 2
kx
00
0 1
00
01
11
10
01
00 10
00 11
00 11
y 1k + 1 y 2
k + 1
(b ) S ta te tab le
(c ) T ransition tab le
x
0
0 1
00
01
11
10
0
0 0
0 1
0 0
z
(d ) O utput m ap
A B C D
0 1x
A
B
D
C
A /0
A /0
A /0
A /0
B /0
C /0
D /1
D /0
y 1ky 2
k
Figure 8.29
SR Realization of the 1111 Recognizer
x
d
0 1
00
01
11
10
1
1 1
1 0
d 0
R 2
x
d
0 1
00
01
11
10
d
d 0
1 0
1 0
R 1
y 1ky 2
kx
0
0 1
00
01
11
10
0
0 1
0 d
0 d
S 1
x
0
0 1
00
01
11
10
1
0 0
0 d
0 1
S 2
y 1ky 2
k
y 1ky 2
k y 1ky 2
k
Figure 8.30
Clocked T and JK Realizations of the 1111 Recognizer
x
d
0 1
00
01
11
10
d
d d
1 0
1 0
K 1
x
0
0 1
00
01
11
10
1
1 1
1 0
0 1
T 2
y 1ky 2
kx
0
0 1
00
01
11
10
0
0 1
1 0
1 0
T 1
x
0
0 1
00
01
11
10
0
0 1
d d
d d
J 1
x
d
0 1
00
01
11
10
d
1 1
1 0
d d
K 2
x
0
0 1
00
01
11
10
1
d d
d d
0 1
J 2
y 1 y 2
x
0
0 1
00
01
11
10
0
0 1
0 1
0 1
Y 1
y 1
y 1 y 2
x
0
0 1
00
01
11
10
1
0 0
0 1
0 1
Y 2
y 2
(a ) C lock ed T exc ita tion m aps
(b) C lock ed JK exc ita tion m aps
(c ) E xcita tion K -m aps
y 1ky 2
k
y 1ky 2
ky 1ky 2
k y 1ky 2
ky 1ky 2
k
Figure 8.31
Clocked JK Flip-Flop Realization of a 1111 Recognizer
C lock
x
z
C
J 1
K 1
y 1Q
Q
y 2C
J 2
K 2
Q
Q
Figure 8.32
Design of a 0010 Recognizer
(d )
C om e h ere for a nin correc t in p u t x = 0
C om e h ere for a nin correc t in p u t x = 1
A B C D E0 /0
G
F
0 /0 1 /0 0 /1
0 /0
1 /01 /0
0 /00 /00 /0
1 /01 /0
1 /0
1 /0
A B C D E0 /0
G
F
0 /0 1 /0 0 /1
0 /0
1 /01 /0
0 /0
1 /01 /0
(c )
A B C D E0 /0
G
F
0 /0 1 /0 0 /1
1 /01 /0
0 /0
1 /01 /0
(b )
A B C D E0 /0
G
F
0 /0 1 /0 0 /1
(a )
0 1x
A
B
C
D
G
B /0
C /0
G /0
B /1
G /0
A /0
A /0
D /0
A /0
A /0
0 1x
A
B
C
D
E
F
G
B /0
C /0
G /0
E /1
C /0
B /0
G /0
F /0
F /0
D /0
F /0
F /0
F /0
F /0
(e ) (f)
0 /0
1 /0
1 /0
A B C D1 /0
G
0 /0
1 /0
0 /1
0 /0 1 /00 /0
(g )
Figure 8.33
Design of a Serial Binary Adder
(d )
C
QD
a i
b i
C i
S i
C i-1
C lock
0 0 /00 1 /11 0 /1
11 /0
0 0 /1
0 1 /01 0 /011 /1
c i-1 = 0 c i-1 = 1
a ib i/s i
(b )
0 1
a i b i c i-1
00001111
00110011
01010101
00010111
01101001
c i s i
(c )
(a )
S h if t reg is te r AS er ia la d d erb i
s i
S h if t reg is te r B
a i
Figure 8.34
Design of a Four-State Up/Down Counter
(a ) S ta te d iagram
z = 0
0 1
23
z = 3
10
z = 1
z = 2
0 1x
0
1
2
3
1 /0
2 /1
3 /2
0 /3
3 /0
0 /1
1 /2
2 /3
(b ) S ta te tab le
y 1ky 2
k
y 1k + 1 y 2
k + 1
0 1x
0 0
0 1
11
1 0
0 1
1 0
0 0
11
11
0 0
1 0
0 1
(c ) T ransition tab le
y 1 y 2
x
0
0 1
0 0
0 1
11
1 0
d 1 d
1 d 0 d
d 1 d 0
d 0 d 1
J 1 K 1 J 1 K 1
(d ) E xc ita tion m aps
y 1 y 2
x
1
0 1
0 0
0 1
11
1 0
d 1 d
d 1 d 1
d 1 d 1
1 d 1 d
J 2 K 2 J 2 K 2
1 0
01
10
Figure 8.35
An Implementation of the Up/Down Counter
C lock
1
L E D s
y 2
x Q
Q
C
J 1
K 1
y 1
Q
Q
C
J 1
K 1
Figure 8.36
Design a BCD Counter
(a )
(b )
x
x
y 3k y 2
k y 1k y 0
k
0 0 0 0
0 0 0 1
0 0 1 0
0 0 11
0 1 0 0
0 1 0 1
0 11 0
0 11 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 11
11 0 0
11 0 1
11 1 0
11 1 1
0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 11
0 1 0 0
0 1 0 1
0 11 0
0 11 1
1 0 0 0
1 0 0 1
d d d d
d d d d
d d d d
d d d d
d d d d
d d d d
1
0 0 0 1
0 0 1 0
0 0 11
0 1 0 0
0 1 0 1
0 11 0
0 11 1
1 0 0 0
1 0 0 1
0 0 0 0
d d d d
d d d d
d d d d
d d d d
d d d d
d d d d
y 3k + 1y 2
k + 1y 1k + 1y 0
k + 1
0
1
2
3
4
5
6
7
8
9
0
0
1
2
3
4
5
6
7
8
9
1
1
2
3
4
5
6
7
8
9
0
Figure 8.37 (a) and (b)
Design of the BCD Counter (con’t)
(c )
x0
0
0
0
0
0
0
0
0
d
d
d
d
d
d
d
d
1
0
0
0
0
0
0
0
1
d
d
d
d
d
d
d
d
0 0 0 0
0 0 0 1
0 0 1 0
0 0 11
0 1 0 0
0 1 0 1
0 11 0
0 11 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 11
11 0 0
11 0 1
11 1 0
11 1 1
y 3k y 2
k y 1k y 0
k
J 3
x0
d
d
d
d
d
d
d
d
0
0
d
d
d
d
d
d
1
d
d
d
d
d
d
d
d
0
1
d
d
d
d
d
d
K 3
x0
0
0
0
0
d
d
d
d
0
0
d
d
d
d
d
d
1
0
0
0
1
d
d
d
d
0
0
d
d
d
d
d
d
J 2
x0
d
d
d
d
0
0
0
0
d
d
d
d
d
d
d
d
1
d
d
d
d
0
0
0
1
d
d
d
d
d
d
d
d
K 2
x0
0
0
d
d
0
0
d
d
0
0
d
d
d
d
d
d
1
0
1
d
d
0
1
d
d
0
0
d
d
d
d
d
d
J 1
x0
d
d
0
0
d
d
0
0
d
d
d
d
d
d
d
d
1
d
d
0
1
d
d
0
1
d
d
d
d
d
d
d
d
K 1
x0
0
d
0
d
0
d
0
d
0
d
d
d
d
d
d
d
1
1
d
1
d
1
d
1
d
1
d
d
d
d
d
d
d
J 0
x0
d
0
d
0
d
0
d
0
d
0
d
d
d
d
d
d
1
d
1
d
1
d
1
d
1
d
1
d
d
d
d
d
d
K 0
Figure 8.37 (c)
Realization of the BCD Counter Design
Figure 8.37 (d) and (e)
y 1k y 0
k
y 2k y 3
k
0
0 0 0 1 11 1 0
0 0
0 1
11
1 0
d d 0
0 d d 0
0 d d d
0 d d d
x = 0
0
0 0 0 1 11 1 0
d d 0
0 d d 0
1 d d d
0 d d d
x = 1(d )
C lock
L ig h ts
x
y 2 J 2
K 2
C
y 1 J 1
K 1
C
y 0 J 0
K 0
C
(e )
y 3 J 3
K 3
C
K-map For Y1 in Example 8.16
0
y 2
y 0
0 d 0
0 0 d 0
1 1 d d
1 1 d d
y 3
y 1
0
y 2
y 0
0 d 0
1 1 d 0
0 0 d d
1 1 d d
y 3
y 1
y
Figure 8.38
Robot Controller Floor Plan -- Example 8.17
E xit
M ovableb lock s
B ottom viewof robot
R obot
W heels
Sensor(X )
Figure 8.39
Robot Controller Design
Figure 8.40 (a) -- (e)
y 1 y 2
(a )N S /z 1 z 2
0 /001 /01
X /Z 1 /Z 2
A B
CD
0 /00
1 /101 /10
0 /00
1 /01
0 /00
0 1x
A
B
C
D
A /00
C /00
C /00
A /00
B /01
B /01
D /10
D /10
Y 1 Y 2 /z 1 z 2
0 1x
00
01
11
10
00/00
11 /00
11 /00
00/00
01/01
01/01
10/10
10/10
(b) (c )
0 0
0 0
0 1
0 1
0 1x
00
01
11
10
0 1
0 1
0 0
0 0
0 1x
00
01
11
10
0 0
1 0
1 1
0 1
0 1
00
01
11
10
z 1 z 2 Y 1
0 1
1 1
1 0
0 0
0 1x
Y 2
(d ) (e )
00
01
11
10
x
y 1 y 2
y 1 y 2 y 1 y 2 y 1 y 2 y 1 y 2
Robot Controller Realization
x
C lock
Q 1
Q 1
J 1
Q 2
Q 2
J 2
K 1
K 2
z1
z2
(f)
Figure 8.40 (f)
Candy Machine Controller Design -- Example 8.18
NC oin
detector
R
C(a )
(b )
N D /R C
00/00
00/00
00/00
10/10 ,01 /11
10/00
01/10
C ontrolun it
R eleasecandy
R eleasechange
D
10/00
10/00
01/00
1015
05
00/00
01/00
Figure 8.41
Algorithmic State Machines (ASMs)
0 1
(a) (b ) (c )
S tate_N am e
M oore outputsInput
M ealyoutputs
Figure 8.42
ASM Representation of a Mealy Machine
0 1
z = 0
X
0
1 0
z = 0
X
z = 1
z = 0
X
z = 0 z = 1
1
A
B
C
(a )
1/0
1 /1 1 /00 /0
C
AB
0/10 /0
(b)
X /Y
Figure 8.43
ASM Representation of a Moore Machine
0 1X
0
0 1X
X1
Az = 0
Bz = 1
Cz = 0
1
00
C /0
A /0B /110
(a )
(b )
1
Figure 8.44
Eight-Bit Two’s Complementer ASM -- Example 8.19
Figure 8.45
0
z = 0
x
1
z = 1
x
z = 0
0
z = 1
1
BC om plem ent
rem ain ing b its
AL ook forfirst 1 b it
Binary Multiplier Controller -- Example 8.20
Figure 8.46
R eg is te r A
R eg is te r M
0
4
M u lip lie r
2 -b itcou n ter
C o u t
A d d er P rod u c t
H a ltC on trol
u n it
C 0Q 0
S u m
A d d
S h ift
R eg is ter con trol s ig n a ls
S ta r t A d d S h ift
0
R eg is te r Q
4 4
4
4
M u lip lica n d4
4
1Q 0
0C 0
S ta r t
1
H a lt
A 0M M u lt ip lie rQ M u lt ip lica n dC N T 0
S h if t r ig h t A : QC N T C N T + 1
A A + M
H a lt 1
(a ) (b )
One-Hot State Assignments
Sequential Assignment One-hot AssignmentState y1y0 y3y2 y1y0
A 00 0001B 01 0010C 10 0100D 11 1000
Table 8.1
ASM Design Using One-Hot State Assignments
Figure 8.47 (a) -- (b)
A
B
S ta te A
B egin C lock
(a)
D A
Q A
C
S ta te B
D B
Q B
C
S ta te A
S ta te B
S ta te C
...
B
C lock
D A
Q A
C
D B
Q B
C
... ...
C
D C
Q C
C
A
(b )
ASM Design Using One-Hot Assignments (con’t)
Figure 8.47 (c)
M ooreou tp u t
z = 1 M ea lyou tp u t
0 1In p u ts
S ta te A
S ta te B
S ta te C
C lock
D A
Q A
C
A
D A
Q B
C
z
D A
Q C
C
x
(c )
One-hot Design of A Multiplier Controller -- Example 8.21
Figure 8.48
C lock
D A
Q A
C
D B
Q B
C
D D
Q D
C
D C
Q C
C
B eg in
S ta r t
A d d
Q 0
H a lt
C 0
S h ift
C lock
D B
Q B
C
B eg in
z
x
S ta r t
D A
Q A
C
(a )
(b )
Incompletely Specified Circuits -- Detonator (Example 8.22)
x zD etonator
(a ) (b )
1 /0 1 /0 1 /0 1 /1
0 1x
A
B
C
D
A /0
-/-
-/-
-/-
B /0
C /0
D /0
-/1
(c )
0 /0
A B C D -
Figure 8.49
Detonator Example K-maps
y 2y 1
x
00
0 1
00
01
11
10
01
d d 10
d d d d
d d 11
y 2k + 1y 1
k + 1
x
0
0 1
00
01
11
10
0
d 0
d 1
d 0
z
x
0
0 1
00
01
11
10
0
d 1
d d
d 0
T 2
x
0
0 1
00
01
11
10
1
d 1
d d
d 1
T 1
y 2y
1
y 2y
1
y 2y
1
Figure 8.50
Detonator Realization
C lock
x
C
T 1
zy 1 y 2
Q
Q C
T 2 Q
Q
Figure 8.51
Sate Assignments and Circuit Realization
(a )
Y 2Y 1/z D 2
0 1x
0 0
0 1
11
1 0
0 d /1
1 0 /0
d d /0
d d /d
0 0 /0
0 0 /0
1 0 /1
0 1 /1
x
1
0 1
0 0
0 1
11
1 0
d 0 0
1 0 0 0
d d 1 0
d d 0 1
x
1
0 1
0 0
0 1
11
1 0
0
0 0
0 1
d 1
z D 1 D 2 D 1
T 2
x
0
0 1
0 0
0 1
11
1 0
d 0 0
1 1 0 1
d d 0 1
d d 1 1
T 1 T 2 T 1 J 2
x
0
0 1
0 0
0 1
11
1 0
d 0 d
1 d 0 d
d d d 0
d d d 1
K 2 J 2 K 2 J 1
x
d
0 1
0 0
0 1
11
1 0
d 0 d
d 1 d 1
d d d 1
d d 1 1
K 1 J 1 K 1
(b ) (c )
(d ) (e )
y 2y 1
y 2y 1 y 2y 1
y 2y 1 y 2y 1 y 2y 1
Figure 8.52