a cmos soi, cdma low noise amplifier · 2020. 4. 8. · a 1-v, cmos on soi, 1.9-ghz cdma low noise...

A 1-V, CMOS on SOI, 1.9-GHz CDMA Low Noise

Amplifier

by Heng Jin

A thesis submitted in conformity with the requirements for the degree of Master of Applied Science

Department of Electrical and Computer Engineering UniversiSr of Toronto

2000

O Copyright by Heng Jin 2000

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A 1-V, CMOS on SOI, 1.9-GHz CDMA Low Noise Amplifier

Master of Applied Science. 2000

Heng Jin

Department of Electrical and Computer Engineering

University of Toronto

Abstract

This thesis deals with the design and implernentation of a IV, 1.9GHz low noise

amplifier (LNA) using a 0.5pm CMOS on SOI technology with 3 levels of metal. The

arnplifier is optimized for CDMA applic2tions operating in the 1.93- 1.99GHz band. The

inductive degeneration topology used in the LNA implementation provides low noise and

low power dissipation. The use of CMOS on SOI rechnology may lead to an optimum

single chip implementation of both the analog and digital building blocks of a 1.9GHz

transceiver operating from a IV supply. Such an implementation offers reduced cost and

improved reliability.

The LNA consists of two amplifying stages with on-chip inductors and capacitors. At

1.96GHz, the arnplifier has a 1.9d.B noise figure, a 14dB gain and a 3dBm IIP3. It also

exhibits 17.4dB input and 28.3d.B output renirn losses respectively in a 50R system without

extemd matching networks. The circuit draws 10.6mW from a IV supply and the chip area

is 1.1~24 mm2.

Acknowledgments

I would like to express my sincere gratitude to Professor C.A.T. Salama for his

insightful guidance and invaluable assistance throughout the course of this work.

My sincere thanks to Jaro Pristupa for his technical assistance. My appreciation

extends to al1 the staff and students in the Microelectronic Research Laboratory including

Dana Reem, Anthoula Kampouris, Milena Khazak, Richard Barber, Dod Chettiar, Eck

Kubowicz, Mehrdad Rarnezani, Dusan Suvakovic, Homoz Djahanshahi, John Ren,

Farhang Vessai. Sotoudeh Hamedi-Hagh. Naoto Fushijima. Sameh G. Nassif-Khalil and

Koji Yano for a11 their help.

1 would like to thank my friend. Song Ye, who kept me Company with his constructive

discussions and cheerful chats, and the test of my friends: Louis Zhang, S e m Hsien-en

Peng, Jianghong Hu, Yucai Zhang, Shuo Chen, Franklin Zhao, Zhixian Jiao, Wei Yang,

Derek Hing Sang Tarn and Hongfei Lu who were always there for me.

A special word of thanks to rny parents and my sister who have been a constant source

of support and encouragement.

And to my wife Wei An, thank you for your patience, support and love. To my daughter

Dian Jin, for being the best baby a father could have.

This work was supported by NSERC, Micronet, Gennum. Mitel, Norte1 Networks and

PMC-S ierra.

Table of Contents

Page

7 1.1 The Role of the LNA in Wireless Receivers ............................................................ 1.2 Fundamental Characteristics of Low Noise Amplifiers ........................................... 3

............................................................................................................ S-parameters 3 Noise Figure ............................................................................................................. 5 Third-order Intermodulation Intercept Point Referred to the Input (IIP3) .............. 5

1.3 Why CMOS on SOI ................................................................................................. 7 ...................................................................................... 1.4 CMOS LNA Architectures 7

Resistive termination ............................................................................................... 8

............................................................................................. S hun t-series feedbac k 9 Inductive degeneration ............................................................................................ -9

1.5 Previous Work on CMOS LNA ..................... ...... .................................................... 9 1.6 Thesis Objective and Outline ................................................................................. IO

CHAPTER 2 Design of a Low Noise Amplifier for Wireless Transceivers ..mm..a....a.... 13

Introduction ............................................................................................................ 13 Classical Two-Port Noise Theory .......................................................................... 13 2.2.1 Noise figure and two-port noise parameters ................................................. 14 2.2.2 Optimum source admittance ...................................................................... 16

................................................................................................ Noise in MOSFETs 17 Derivation of the MOSFET Two-Port Noise Parameters ...................................... 19 Power-Constrained Noise Optirnization ................................................................ 22 LNA Design ........................................................................................................... 25 LNA Layout ........................................................................................................... 27 2.7.1 Transistor layout ........................................................................................... 28 2.7.2 Capacitor layout ............................................................................................ 28 2.7.3 Inductor layout .......................................................................*...................... 29 2.7.4 Final Layout ..................................... ........................................................... 30

iii

2.8 Post-Layout Simulation Results ............................................................................. 3 1 ...................................................................................................... S-parameters 32

..................................................................................................... Intermodulation -33 ................................................................................................................. S tability 34

...................................................................................................................... Y ield -34 .............................................................................................. Temperature effects -34

2.9 Summary ................................................................................................................ 35

............................................... CHAPTER 3 Experimental Results .oooo.ooooooo.ooooooooooomoooooo37

...................................................................................... 3.1 The LNA Implementation 37 .......................................................................................................... 3.2 LNA Testing 38

3.2.1 Gain and noise figure .................................................................................... 38 .................................................. 3.2.2 Reflection coefficient and reverse isolation 39

........................................................................ 3.2.3 Intermodulation distortion 1 .......................................................................... 3.2.4 Performance characteristics 42

................................................................................................................ 3.3 Summary 42

CHAPTER 4 Conclusions ...............................................................D............................ c.45

List of Figures

Page

7 . Fig 1 . 1 . Portable PCS receiver architectures ...................................................................... Fig . 1 2: LNA connected as a two-port network for S-parameten characterization .......... 4 Fig . 1.3. Amplifier input versus output characteristics ....................................................... 6

.................................................................................... Fig . 1.4. CMOS LNA architectures 8 Fig . 2.1 : Cascaded noisy stages ........................................................................................ 13 Fig . 2.2. Equivalent noise mode1 for noisy two-port dnven by noisy source ................... 14 Fig . 2.3: Noise circuit model for the MOSFET . (a) Conventional mode1 .

(b) Mode1 with al1 noise sources refiected to the input ....................................... 18 Fig . 2.4. Dependence of NF on Qs as a function of power dissipation ............................. 24 Fig . 2.5. Inductive 1 y degenerated common-sourced amplifier ......................................... 25 Fig . 2.6. Low noise amplifier schematic ........................................................................... 27 Fig . 2.7. Transistor layout ................................................................................................. 28 Fig . 2.8. Capacitor layout .................................................................................................. 29 Fig . 2.9. Typical inductor layout ....................................................................................... 30 Fig . 2.10. Final full circuit layout ..................................................................................... 31 Fig . 2.1 1 : Final circuit schematic for the LNA ..................... .. ................................ 31 Fig . 2.12. S-parameters venus frequency for the LNA .................................................... 32 Fig . 2.13. LNA output spectrum using a two-tone RF input ............................................ 33 Fig . 3.1 : Micrograph of the LNA ...................................................................................... 37 Fig . 3 . 2 Test setup for gain measurements ...................................................................... 38 Fig . 3.3. Test setup for noise figure measurements .......................................................... 38 Fig . 3.4. Gain and noise figure versus frequency for the LNA ......................................... 39 Fig . 3.5. Test setup for S-parameter measurements .......................................................... 39 Fig . 3.6. (a) Input and (b) output reflection coefficients for the LNA .............................. 40 Fig . 3.7. Reverse isolation (S 12) for the LNA ................................................................... 40 Fig . 3.8. Test senip for two-tone third-order intermodulation rneasurements .................. 41 Fig . 3.9. Measured LNA output spectrum ........................................................................ 41

List of Tables

Page

Table 1.1. Surnmary of recentiy reported CMOS LNA characteristics ............................ 10 Table 2.1 : Simulation results of LNA at different temperatures ....................................... 35 Table 3.1 : Summary of LNA characteristics (25OC) ......................................................... 42 Table 3.2. Measured performance and cornparison with previous design ........................ 43

Chapter 1 : Introduction 1

HAPTER 1

Introduction

The analog front-end in a wireless transceiver acts as the interface between the antenna

and the digital signal processor. In the digital signal processor, low power is essential,

making submicron CMOS technology the best implementation choice. The analog front-

end and specifically the low noise amplifier (LNA) require a high speed technology, such as

GaAs or silicon bipolar. However, the use of low-cost submicron CMOS or SOI CMOS

technology in the analog front-end may lead to an optimum single chip implementation of

both the analog and digitai building blocks in wireless transceivers used in modem high

capacity mobile communication systems. Such an implementation ofters reduced cost and

improved reliability.

SOI CMOS provides a variety of advantages over bulk CMOS, such as reduced

parasitic capacitance and elimination of backgating. Moreover, SOI devices exhibit high

speed performance even at low supply voltage (-IV). Furthemore, due to the low-loss

dielectric substrate, SOI inductors have higher self-resonant frequencies and higher quality

factors than those fabricated on bulk silicon.

This thesis descnbes a IV, 0.5pm SOI CMOS LNA optimized for CDMA applications

and operating in the 1.93-1 -99GH.z band. Compared to previously reported designs [9, 10,

12, 131, the present design offers Iower noise, high gain, low intermodulation distortion and

onthip 500 input output impedance rnatching.

A l-V, CMOS on SOI, 1 .!&GHz CDMA Low Noise Amplifier University of Toronto


1.1 The Role of the LNA in Wireless Receivers

In a wireless receiver, the information being relayed is either voice or data which is

used to modulate a radio frequency (RF) carrier. Narrowband circuitry in the radio

transceiver is used to access the portion of the frequency spectrum that has been allocated

for the communications service. For example, the 1930-1990 MHz band is used by the

North Amcricm CDMA standard for the PCS (Persona! Communication Semices)

Receiving (Rx) band.

PCS offers the following advantages over conventional cellular service: (1) PCS is an

dl-digital system from its inception, (2) PCS allows for wireless voice. data, and video

transmissions, and (3) PCS has searnless roaming in North America.

Antenna

RF mixer IF amplifier IF mixer Data out

(a) Heterodyne receiver

'XI +%+

rXI

Bandpass filter Image-reject filter

Antenna

Bandpass filter

Bandpass filter 1 Low-pass filter

rL 'XI

kz l (b) Homodyne receiver

Fig. 1.1 : Portable PCS receiver architectures

+ LNA 'XI

A 1 -V, CMOS on SOI, t .%GHz CDMA Low Noise Amplifier University of Toronto

rL 'XI De-rnodulator


The two receiver architectures that are considered viable for portable PCS applications

are shown in Fig. 1.1. The conventional superheterodyne (heterodyne or dual-conversion)

receiver illustrated in Fig. 1.1 (a), uses a high quaiity bandpass filter centered at an

intermediate frequency (IF) to select the desired communications channel. The radio

frequency signal received at the RF input to the mixer is multiplied by the local oscillator

(LO) signal and it is thereby translated to an intermediate frequency (IF) band. This

facilitates signal processing at a lower frequency where higher quality filters and arnplifiers

can be economicaily constructed.

The direct-conversion or homodyne architecture, illustrated in Fig. 1.1 (b), is an

alternative to the heterodyne scheme. The signal from the antenna is directly convened to

the baseband where al1 of the filtering must be done to select the desired channel.

It should be noted that in the RF section of the receivers, the low-noise amplifier is

cornmon to both the heterodyne and homodyne schemes. In the conversion process from the

RF to the IF bands, the received signal is degraded by the noise from the mixers, and

consequently low-noise prearnplifiers are placed ahead of the mixers in the receive chahs to

improve the signal to noise ratio.

1.2 Fundamental Characteristics of Low Noise Amplifiers

The main characteristics of low noise arnplifiers are discussed in the following

paragraphs.

S-parameters

S-parameters cm be used to characterize the performance of a LNA. Szl is the gain of

the LNA when its input and output impedances are rnatched to 50Q . S and S22 are used to

A 1-V, CMOS on SOI, 1.9-GHz CDMA Low Noise Amplifier University of Toronto

Chapter 1: Introduction 4

c harac tenze the input and output impedance matching respectively. S 2 represents the

reverse isolation of the LNA.

- * * -

Er1 - * -En : 11 '2 : R1=50!2 -?y- LNA

4" 8 * A

I Y I

* 1

~eferen& Plane 1 Reference Plane 2

Fig. 1.2: LNA connected as a two-port network for S-parameters characterization

A block diagram of the LNA connected as a two-port network for S-parameters

characterization is shown in Fig. 1.2. The forward transmission coefficient S2, (also cailed

power gain or simply gain), is related to the terminal voltages V? and El by the fonvard

voltage gain (A,,), and is given by the following equation

l m ICI Power delivered to the Ioad

V? A, = - ( 1 2) El

and resistances RI and R2 are the source and load impedances, which are typically 5042

S 7 , can be interpreted as twice the voltage gain (A,,) developed between the load (V2) and

the opencircuited source voltage (El) , when R1=R2.

Similady, the reverse voltage gain is related to SIZ (IS 121 is also called reverse isolation)

by the equation:

Power delivered to the source - - Power available from the load

A 1-V, CMOS on SOI, 1 .%GHz CDMA Low Noise Amplifier University of Toronto


The remaining S-parameters: SI and S2*, define the input and output reflection

coefficients of the two port network, and are related to input (2,) and output impedances

(ZouJ of the LNA respectively and the characteristic impedance of the test system. Zo, by

the following equations

- - Power delivered to the input - Zin - Z~ ' i n - I - - - Power available from the source Zin + Zo Zin + Ri Power delivered to the output - Z ~ ~ t - Z ~ - Z ~ ~ t - Rz

SZ2 = - - Power available from the load Z,,, + Zo Z,,, + R2 Noise Figure

The noise figure (NF) is used to specify degradation in the signal-to-noise ratio caused

by the LNA and it is always expressed in dB. The noise factor F is the linear equivalent of

the noise tigure, and it is given by the following expression

Input signal-to-noise ratio - F= - Total output noise Output signal-to-noise ratio Total output noise due to the source ( 1.7)

Noise and the way to reduce the NF in the LNA are discussed in Chapter 2.

Third-order Intermodulation Intercept Point Referred to the Input (m3)

While noise puts a limit on the lower Ievel of the signal which c m be received, an upper

limit is imposed by the finite power supply voltage used for active circuits and the non-

linear transfer characteristic inherent in the semiconductor devices. As the input signal

increases in amplitude, these limitations cause distortion, compression and saturation of the

signal being processed by the amplifier. Intermodulation distortion caused by non-

linearities of the active components cm result in spurious distortion being generated within

the receive channel bandwidth in a narrowband application. In such cases, the interference

caused by the distortion products can be mistaken for the desired signai.

A t -V, CMOS on SOI, 1 -9-GHz CDMA Low Noise Amplifier University of Toronto


Even-order intermodulation products are normally found at frequencies well above or

below the signals which generated them and are usually of Iittle concern. The odd-order

distortion produced by an LNA c m give rise to distortion products which c m rnask or

interfere with the desired signal. The third-order products are the most significant and c m

lie very close to the signals which generated them in frequency. Third-order non-Iinearîiy is

customa-ily characterized by a specification called the third-order intercept point.

Input Power

Fig. 1.3: Amplifier power output venus power input characteristics

Fig. 1.3 illustrates the relationship between the fundamental and intermodulation

distortion products generated by an amplifier for two equal amplitude input signals at

different frequencies. The upper line shows the relationship between the fundamental

output and the input signal (i.e., the gain), which is linear (1:l dope) at low input power

A I -V, CMOS on SOI, 1 .%GHz CDMA Low Noise Amplifier University of Toronto


levels, but rolls-off or compresses at high input power levels. The third order

intermodulation lies well below the fundamental or linear curve at lower input powers, but

increases with a 3: 1 slope for increasing input power. The fundamental and intermodulation

distortion curves c m be extrapolated to a point of intersection, which is called the third-

order intercept point. The intercept point cm be referred to either the input or output power

axes; then respective points are known as the third-order intercept point referred to the input

(IIP3) or to the output (OIP3).

1.3 Why CMOS on SOI

In this work. CMOS on SOI is used to implement the LNA. SOI CMOS provide a

variety of advantages over bulk CMOS such as reduced parasitic capacitance and

elimination of backgating. Moreover, SOI devices exhibit high speed performance even at

low supply voltage (-IV). Furthemore, due to the low-loss dielectric substrate, SOI

inducton have higher self-resonant frequencies and higher quality factors than those

fabricated on bulk silicon. The inductors fabricated on silicon suffer substrate losses, which

are caused by both inductive and capacitive coupling between the inductor metal Iayer(s)

and the conductive substrate.

1.4 CMOS LNA Architectures pl

Much work on CMOS LNA's has been done [2-131. The architectures reported cm be

classified into four distinct types, illustrated in simplified form in Fig. 1.4. Each of these

architectures may be used in a single-ended forrn (as shown), or in a differential form.

Differential architectures require the use of a balun to transform the single-ended signal

from the antenna into a differentid signal. Practical baluns introduce extra loss which adds

directly to the noise figure of the system, so single-ended architectures are preferred.



Zin Zin I

5 L-+ r- T (a) Resistive termination (b) l/g, temination

(c) Shunt-series feedback (d) Inductive degeneration

Fig. 1.4: CMOS LNA architectures

Resistive termination 131

The resistive termination configuration, shown in Fig. 1.4 (a), is also called the

common source configuration. The use of real resistors provides SOC2 input impedance.

However, it results in a noise figure of 3dB or higher, independent of the minimum noise

performance of the transistor. Two effects are responsible for this degradation in noise

figure. First, the added resistor contributes its own noise to the output which equals the

contribution of the source resistmce. Second, the input is attenuated by the resistor.

The common-gate topology, shown in Fig. 1.4 (b), provides good isolation between the

input and output in cornparison to the common source topology. In order to match the input

to SOR, the device transconductance g, have to be set to 1/50Q. The minimum noise figure

in this configuration tends to be around 3dB theoretically and greater in practice.

pp



Shunt-series feedback [5]

LNA design for CDMA transceivers typically requires a noise figure around 2dB. So,

the previously described architectures are not candidates for this application. Fig. i.J(c)

illustrates a topology, which uses resistive shunt and senes feedback, to set the input and

output impedances of the LNA. It is reported [5] that amplifiers using shunt-series feedback

often have high power dissipation compared to others with similar noise performance. The

higher power is partially due to the fact that such amplifiers are naturally broadband. and

hence techniques which reduce the power consumption through LC tuning are not

applicable.

Inductive degeneration [2.4,7-9. 1 1- 131

The fourth topology employs inductive source degeneration, as shown in Fig. 1.4 (d), to

generate a real term in the input impedance. Tuning of the amplifier input becomes

necessary, making this a narrow-band approach. However this requirement is not a

limitation for a CDMA transceiver. This architecture meets the low noise and low power

performance specifications of the application and will be the one used in this thesis.

1.5 Previous Work on CMOS LNA

Table 1.1 summarizes recently reported CMOS LNA results. Most of the designs have

difficulty in simultaneously meeting low noise figure (-2dB), low supply voltage (IV), low

power consumption, low input and output retum loss specifications of CDMA receivers.

A l-V, CMOS on SOT. 1 .g-GHz CDMA Low Noise AmpIifier University of Toronto


Table 1.1 : Summary of recently reported CMOS LNA characteristics

1.6 Thesis Objective and Outline

The main objective of this thesis is to develop a IV, 1.9GHz low noise amplifier with

minimum power dissipation and minimum chip area using a silicon on-insulator (SOI)

CMOS process. The LNA is specifically geared for CDMA receiver application in the 1.93-

I .99GHz band,

The SOI CMOS process used for this project is provided by Peregrine Serniconductor

Corporation. The process is a OSym, double poly CMOS process with maximum unity gain

cutoff frequency fT of SOGHz. This process provides 6 transistor types, difised and

polysilicon resistors, and triple layer metal interconnection [14].

The target specifications of the LNA are listed in Table 1.2. An inductive source

degeneration architecture was chosen to achieve the specifications.

Sheng et al.. 1996 [5]

--


COMA 0 . 8 ~ CMOS

FioIougdran el d i . f G J o iôi 1 A ;pm C:dCS

0.6pm CMOS

0.35pmChIOS

0.25pm CMOS

0.5pm SOI

0.25pm SOI

0 . 8 ~ CMOS

O.6pm SOI

0.2pm SOI

Shaeffer et al.. 1997 [2]

Shahani e t d . 1997 r] Huang et al., 1998 f81

Johnson et aL. 1998 [91

Komurasaki et al.. 1998 [IO]

Floyd et ah. 1999 [Il]

Jin et al.. 1999 (121

Harada et al.. 2000 (131

Shunt-Set. FB

GPS

GPS

GPS

NIA

M A

N/A

PCS

N/A

Ggm-Tùrm.

L-Oegen.

L-Degen.

L-Degen.

L-Degen.

NIA

L-Degen.

L-Degen.

LaOegen.

3.3

3.Û

1.5

1.5

2.5

1.5

1.0

2.7

t .5

1.0

7.5

3.5

3.5

3.8

1.85

2.8

3.6

1.5

3.5

3.5

11 .O

22

22

17

16.2

10

7.0

12.4

23.5

IO

N A

A

-9.3

-6

-7.25

4

6,O

-1.9

NIA

O

36

27

30

12

t6

14

5.0

13.5

M A

19

0.9

%'A

NIA

NIA

-123

-12

NIA

-21

N A

NIA

N/A

û.3

1.5

1.5

0.9

2.4

1.9

0.9

t.8

2

N A

:&*A

-5-15

WA

-9.5

-7.5

N A

-5

NIA

NIA

Chapter 1 : Introduction I l

Table 1.2: Target specifications of the LNA

i Noise figure i e.5dB i

Process

Architecture

Power supply

Gain I 14dB

Target specification

0.5pm CMOS on SOI

Inductive degeneration

I V

1 Power consumption 1 1 Frequency 1 1 -93-1.99GHz 1 1 Input output return loss 1 rl O ~ B 1 Terminal impedances 1

The thesis is organized as follows. Chapter 2 describes die architecture, design and

layout of the LNA. Simulation results are presented. Chapter 3 presents the experirnental

results obtained.

Chapter 4 gives a bief summary of what has been achieved and outlines areas for

future work.



References J. Crols and M. S teyaert, "CMOS Wireless Tronsceiver Design", Kluwer Academic Publishers, 1997.

D. Shaeffer and T. H. Lee, "A lSV, 1 .SGHz CMOS Low Noise Amplifier," IEEE J. Solid-State Circuits, vol. 32, pp.745-759, 1997.

J. Y.-C. Chang, A. A. Abidi and M. Gaitan, "Large suspended inductors on silicon and their use in a 2-pm CMOS RF amplifier, "IEEE Electron Device Lett., vol. 14, pp. 246- 248, 1993.

A.N. Karanicolas, "A 2.7V 900MHz CMOS LNA and Mixer," IEEE J. Solid-State Cir- cuits, vo1.3 1, No. 12, pp. 1939- 1944. 1996.

S. Sheng, L. Lynn, J. Peroulsa, K. Stone and 1. O'Donnell, "A Low-Power CMOS Chipset for Spread Spectrum Communications", lEEE ISSCC, San Francisco, Techni- cal Digest, pp.346-347, 1996.

A. Rofougaran, J. Y.-C. Chang, M. Rofougaran and A. A. Abidi, "A lGHz CMOS RF front-end IC for a direct-conversion wireless receiver," IEEE J. Solid-state Circtiits, ~01.3 1, pp. 880-889, July 1996.

A.R. Shahhani, D.K. Shaeffer and T. H. Lee, " A 12mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver," IEEE J. Soiid-State Circuits, vol. 32, pp. 306 1 -3070, 1 997.

Q. Huang, F. Piazza, P. Onatti and T. Ohguro, "The Impact of Scaling Down to Deep Subrnicron on CMOS RF Circuits," iEEE J. Solid-State Circuits. vol. 33, pp. 1023- 1036, 1998.

R.A. Johnson, P.R. Houssaye, C.E. Chang, P. Chen, M.E. Wood, G.A. Garcia, 1. Lagnado and P.M. Asbeck, "Advanced Thin-Film Silicon-on-Sapphire Technology: Microwave Circuit Applications," IEEE Transactions on Eiectron Devices. vol. 45, pp. 1047- 1054, 1998.

[IO] H. Kornurasaki, H. Sato, N. Sasaki, K. Ueda, S. Maeda, Y. Yamaguchi and T. Miki, "A Sub 1-V SOI CMOS Low Noise Amplifier for L-Band Applications,'' IEEE R F Inte- grated Circuits Symposium, Digest of Technical Papers, pp. 153- 156, 1998.

[ l I] B. A. Floyd, J. Mehta, C. Gamero and Kenneth K. O, "A 900-MHz, 0.8-pm CMOS Low Noise Amplifier with 1.2-dB Noise Figure," IEEE CICC, Digest of Technical Pupers, pp. 66 1-664, 1999.

[12] W. Jin, P.C.H. Chan and C. Hai, "1.5-V 1.8-GHz SOI Low Noise Amplifiers for PCS Receivers," IEEE Int. SOI Conference Pmceedings, pp. 16-17, 1999.

[13]M. Harada, T. Tsukahara and J. Yamada, "0.5-1V 2GHz RF Front-end Circuits in CMOS/SIMOX," IEEE ISSCC, San Francisco, Technical Digest, pp.378-379,2000.

[14] Ultra Thin Silicon (UTSI) Luyuut Rules and Design Manual, Peregrine Serniconductor Corporation, 1998.


Chapter 2: Design of a Low Noise Amplifier for Wireless Transceivers 13

Design of a Low Noise Amplifier for Wireless Transceivers

2.1 Introduction

For a low noise amplifier with a cascade of stages, as shown in Fig. 2.1, the overall

noise figure (NFmmr) cm be obtained in terms of the NF of each stages given by Friis'

equation [ I I

NF, - i NF, - I ......... NFtotal = 1 + ( N F , - 1 ) + - + +

A , A I A2......A (2.1)

( m - 1 )

where A!, A2,--, A, are the unloaded voltage gains of the respective stages and the NF of

each stage is calculated with respect to the source impedance driving the stage. This

equation indicates that the noise contributed by each stage decreases as the gain preceding

the stage increases, implying that the first stage in a cascade is the most critical.

Fig. 2.1 : Cascaded noisy stages

A 1 -V, CMOS on SOI, 1.9-GHz CDMA Low Noise Amplifier University of Toronto

Chapter 2: Design of a Low Noise AmpIifier for WireIess Transceivecs 14

In this chapter, a design strategy for a low noise amplifier (LNA) that balances gain,

input impedance, noise figure, and power consumption is developed by first introducing

power-constrained noise optimization of the input MOSFET, because this transistor is the

most important source of noise in the LNA. The theory, architecture, design and layout of

the LNA as well as simulation results are presented in the following sections.

2.2 Classical Two-Port Noise Theory [2]

2.2.1 Noise figure and two-port noise parameters

Any noisy 2-port network driven by a source that has an admittance Y, and an

equivalent shunt noise current 7s can be represented by a noiseless 2-port network plus a

noise voltage source Zn and a noise current source Tn as illustrated in Fig. 2.2.

r - - - - - - - - - - -

'i- Noisy Two-Port Network I %

Fig. 2.2: Equivalent noise modal for noisy two-port driven by noisy source

#

I - 1

Noiseless 1

The noise figure is defined as

YS

NF = Total output noise power Output noise power due to input source (2.2)

Two-Port Network 1

A calculation based directly on (2.2) requires computing of the total power due to d l

1 i

_1

the noise sources and dividing that result by the noise power due to the input source. An

equivalent and simplet method is to compute the total shortcircuit mean-square noise



current due to the input source. The noise figure of the noisy two-port can then be expressed

In order to accommodate the possibility of correlations between e, and in, in cm be

expressed as the sum of two components

where i , is correlatecl with en, and i,, is not and

where Y, is the correlation admittance.

Cornbining (2.3), (2.4). and (2.5). the noise

i: + li, + (Y, + ~, )e , l ' NF = l

figure becomes

Equation (2.6) contains three independent noise sources, each of which may be treated

as thermal noise produced by an equivalent resistance or conductance (whether or not such

a resistance or conductance actually exits) defined as follows

Using these equivalences, the expression for the noise figure c m be written purely in

terrns of impedances and admittances as


Chapter 2: Design of a Low Noise Amplifier for WireIess Transceivers 16

where each of the admittances Y, and Y, have been decomposed into a sum of a

conductance G and a susceptance B, defined as

The parameten Ge. Be. Rn, and G,, define the noise performance of the two-port

network.

2.2.2 Optimum source admittance

Once a given two-port noise has been characterized by its four noise parameters, the

general conditions for minimizing the noise figure c m be identified from (2.10). Taking the

first derivative with respect to the source admittance (B, and G, respectively) and setting it

equal to zero yields

Hence, to minimize the noise figure, the source susceptance should be made equal to the

inverse of the correlation susceptance, while the source conductance should be set equal to

the value defined in (2.14).

The noise figure corresponding to these choices is found by direct substitution of (2.13)

and (2.14) into (2.10) yielding

The noise figure in ternis of NFmin and the source adminance can be expressed as

A 1 -V, CMOS on S 01, 1 -9-GHz CDMA Low Noise Amplifier University of Toronto


2.3 Noise in MOSFETs [2,3]

Since MOSFETs are essentially voltage-controlled resistors, they exhibit noise.

Detailed theoretical considerations [4] lead to the following expression for the drain current

noise ind in the MOSFET

where k is Boltzmann's constant, T is the absolute temperature in Kelvin, Af is the noise

bandwidth in hem, and gdo is the drain-source conductance at V@. y is typically 1-3 for

s hort-c hannei MOSFETs [SI.

In addition to drain current noise. the thermal agitation of channel charge results in gate

noise. The Buctuating channel potential couples capacitively into the gate terminal, leading

to a noisy gate current. The gate noise current ing can be expressed as [6]

where 6 is the coefficient of gate noise (equal to 1.33 for longchamel devices and 4-6 for

short-channel devices) and the parameter gg is given by [6]

where o is the angular frequency in radians per second and Cg, is gate to source

capacitance.

The gate noise in a MOSFET is partially correlated with the drain noise through a

correlation coefficient c defined as

with the value of c theoretically estimated as j0.395 [6].



An additional source of noise in MOS devices is the noise generated by the distributed

gate resistance 171. This noise source can be modeled by a series resistance in the gate

circuit and an accompanying white noise generator. The distributed gate resistance is given

by V I

where Ro is the sheet resistance of the polysilicon gate, W is the total gate width of the

device, L is the gate length and n is the number of gate fingers used to lay out the device.

The factor of 1112 arises from a distributed analysis of the gate resistance, assuming that

each gate finger is contacted at both ends. By contacting at one end only, this term increases

to 113. In addition, this expression neglects the interconnect resistance used to connect the

multiple gate fingers together. This interconnect is normally routed in a metal layer that

exhibits very low sheet resistance and hence is insignificant. The noise circuit model for the

MOSFET is illustrated in Fig. 2.3 (a). Fig. 2.3 (b) shows the same circuit with the noise

source Tnd reflected to the input and labelled inl and en respectively.

O O drain gate

+ - ' ng g9 Cgs

source O O source

O gate l I I I

source I I I 1

drain

source

Fig. 2.3: Noise circuit model for the MOSFET (a) Conventional model. (b) Mode1 with al1 noise sources reflected to the input

A 1-V, CMOS on SOI, 1 -9-GHz CDMA Low Noise Amplifier University of Toronto


The equivalent input noise voltage generator Zn and current generator Tnl account for the

output noise or dnin current noise Tnd (2.17) are given by

and

2.4 Derivation of the MOSFET Two-Port Noise Parameters

The objective of this section is to correlate the noise circuit model of the MOSFET

presented in Fig. 2.3 to the model of Fig. 2.2.

The total equivalent input noise voltage generator in is given by (2.21). Using (2.7). R,l

is given by - 9

The total equivdent input current noise ln is the sum of the reflected drain noise

contribution Zn/ and the induced gate current noise Ing. The latter consists of two terms, one - ing, is hllly

uncorrelated

w here

correlated with the drain current noise, while the other Tngu is completely

with the drain cunent noise. That is

Hence, 7; in (2.4) is given by

and Tu is



The correlation admittance Y, in (2.5) may be expressed using (2.28) and &, as follows

From equation (2.22). Y, can be expressed as

To express Y, in a more useful form, the gate noise correlation coefficient c (2.20) must

be incorporated. The last term in (2.3 1 ) cm be expressed in tems of cross-correlations by

multiplying both numerator and denorninator by

then avenging each. resulting in

the conjugate of the drain noise current and

Using (2.20), the correlation admittance Y,

where

may be wrinen as



G, and Bc may be obtained by comparing (2.12) and (2.33) resulting in

Using the definition of the correlation coefficient, the induced gate noise rnay be

expressed as follows

The 1 s t term in (2.37) is the uncorrelated portion of the gate noise curent. so that, Gu is

Al1 the four MOSFET two-port noise parameters Rn, G,, Bc, and G,, have been derived

in (2.25), (2.35), (2.36) and (2.39). With these parameters,

rninirnizes the noise figure as well ûs the minimum noise

from (2.13), (2.14) and (2.15) resulting in

B,, = -B, = -o~,,(i + a ICI &) The reai part of the optimum source admittance is

both the source impedance that

figure itself c m be detennined


Chapter 2: Design of a Low Noise Amplifier for WireIess Tmsceivers 22

The width of the input MOSFET must be selected using (2.42), which expresses GoPt

as a Function of gare capacitance. Setting GoPr equal to the source conductance yields the

"optimum" value of Cg,, which, in tum, allows computation of the necessary device width.

The required value of Cg, for a 50R system at 1.96GHz was calculated to be around

3.5pF using y=2,6=4, lcl=0.395, and a4.85. A device large enough to produce the required

value of Cs, wouM bc raughly Imm wide. Furthemorc, ;hc bias currcnt for süch a largc

device would typically be over 100mA. Hence the power consumed would be unacceptably

high for virtually any application, even though the noise figure would correspond very

closely to NFmin. Therefore power-constrained noise optimization must be introduced as

discussed in the following section.

2.5 Power-Constrained Noise Optimization (21

The goal here is io reformulate equation (7.16) in tems of power consumption. Once

an equation is denved, it will be minirnized subject to the conscraint of tixed power and then

solved for the width of the transistor corresponding to this optimum condition.

Because the source susceptance B, is zero and Bopt (2.40) is found to be very cloes to

zero [2], the difference between the two cm be neglected. The expression for the noise

figure reduces to:

Rearranging (2.42) for GoPt to define a parameter QOp, with the dimensions of a quality

factor results in

To accommodate the possibility of operation with source conductances other than Gap, a

sirnilar Q in which Gop, is replaced by Gs (the actual source conductance) can be defined as


Chapter 2: Design of a Low Noise Amplifier for Wireless Tmnsceivers 23

Expressing (2.45) using (2.46) and (2.47), and the noise parameters of (2.25) and (2.34)

results in the following noise figure expression

The pararneters a, g,, Qop, and Q, in (2.48) are linked to power dissipation. To rewrite

these terms directly in terms of power, first recall that an expression for the drain current is

191 7

P- b = w L C ~ ~ v ~ a t E s a t r + P (2.49)

where

and

where Cm is the gate oxide capacitance per unit area, v,,, is the saturation velocity, and E,,

is the velocity saturation field strength. p, is the electron rnobility.

The power dissipation can be written as follows

Furthemore, the transconductance g, c m be found by differentiating (2.49). After

rearranging, this may be expressed as:

Cg, c m be expressed as:

Substituting for Cm from (2.52) results in

A 1-V, CMOS on SOI, 1 .%GHz CDMA Low Noise Amplifier University of Toronto

Chapter 2: Design of ri Low Noise Amplifier for Wueless Transceivers 24

and

where

Wth the aid of ihese expressions, the noise figure (2.48) cm be written in ternis of p

and PD. Minimizing the resulting equation is complex enough but it is best solved

graphically as shown in Fig. 2.4. From this figure. it can be concluded that the value of QSp

that leads to the power-constrained minimum noise figure is between 3.5 and 5.5.

Fig. 2.4 : Dependence of NF on Qs as a function of power dissipation, for L=0.5pm, Rb5011, (u=2d=2m1.96GHz, Vdd=l V, ~2.5, 6=5.0, ld=0.395, v S a ~ l XI 05m/s, and ~ ~ ~ ~ 4 . 7 ~ 1 06v/rn

Once Qsp has been determined, the width of the optimum device c m be expressed

using (2.54) and (2.56) resulting in

- - - - - - - -- - - - - - - - -



With a device of width WVtp the noise figure obtained using (2.48) is

This noise optimization method is used in the design because it accounts for al1 the

parameters of interest. An exceilent input match can be achieved, as discussed in next

section by the inductive source degeneration technique, while providing nearly the best

noise figure possible in a given technology with a specified power dissipation. For

W=2nfi2m 1.96GHz, L=0.5pm, C,,=2.79x 1 o - ~ F / ~ ' , RS=50R and QSp=4.5, WqrP is found

from (2.58) to be 3961m.

2.6 INA Design

As described in Chapter 1, inductive degeneration topology as shown in Fig. 2.5 (a)

meets the low noise and low power performance specifications of the LNA and will be used

in this thesis. The LNA was designed in a 0.5pm CMOS on SOI technology with 3 levels of

Fig. 2.5: lnductively degenerated common-sourced amplifier

Assuming the device mode1 with only a transconductance and a gate-source

capacitance as shown in Fig. 2.5 (b) [IO], the input impedance Zin has the following form


Chapter 2: Design of a Low Noise Amplifier for Wireless Tmnsceivers 26

At resonance, Zin becomes Zin = a&s (3.6 1 )

At resonance, the impedance is purely real and proportional to L,. By choosing L,

appropriately, the real term can be made equd to 5OR The gate inductance Lg is used to set

the resonance frequency once L, is chosen to satisw the criterion of a SOC2 input impedance.

It is important to emphasize that L, does not generate thermal noise.

In an amplifier specification where the necessary gain cannot be obtained in one stage.

the logical step is to try a multistage design, allowing the desired gain to be spread over

multiple stages, reducing the gain for each stage to a value that c m be achieved in one stage.

As (2.1) suggests, only the NF of the first stage plays a criticai role. So, the design

procedure developed in the previous section can be used for that stage. Fint, (2.58) is used

to determine the necessary device width. Then, the device is biased using the arnount of

current allowed by the power constraint. Next. the value of the source inductance L, is

chosen to provide the desired input match, using the value of CO, that corresponds to the bias

conditions. The expected noise figure can then be computed from (2.59). Findly, sufficient

inductance Lg is added in series with the gate to bring the input loop into resonance at the

desired openting frequency.

In this design, a two-stage amplifier topology with inductive degeneration at the source

was used as illustrated in Fig. 2.6. Inductive source degeneration offers simultaneously

optimal noise and impendance matching. In addition. good lineaity is achieved. On-chip

spiral inductors were used to provide input and output matching and to act as loads in the

two stages of this design. Lbl and LM provide both matching and gate bias simultaneously.

Capacitor Ci, Cc and Co are used for both matching and DC decoupling. MI and M2 are

intrinsic N channel MOSFETs with OV threshold voltage. The topology allows the amplifier

to operate at a IV supply voltage V' A gate width of 396pm for Ml was chosen to

optimize the noise figure and minirnize DC power dissipation. The gaie width M2 was

chosen the same as Ml, because the two stages can be biased by a simple bandgap circuit


Chapter 2: Design of a Low Noise Amplifier for WieIess Transceivers 27

without increasing the power consumption. Circuit simulations were carried out using

Agilent's Advanced Design System (ADS) to determine the optimal values of the remaining

components in the circuit. These values are given in Fig. 2.6. The bias voltage Vbias is

generated off-chip for flexibility in testing.

Fig. 2.6: Low noise amplifier schematic

Careful layout of the LNA was necessary to meet the low noise and high frequency

performance specifications. An appropriate layout not only maximizes the yield but also is

the only way to achieve the required specifications predicted by simulations. Care must be

taken to minimize resistive Iosses associated with metai lines and to ensure that other losses

in the circuit do not diminish the overall performance of the circuit.

A 1-V. CMOS on SOI, 1 -9-GHz CDMA Low Noise Amplifier University of Toronto


2.7.1 Transistor layout

The layout of the transistor must ensure that the distributed gate resistance does not

adversely impact the noise figure. By interdigitating the device with each gate finger

contacted at both ends, the contribution of this source of noise can be reduced to

insignificant levels. The interconnect was routed in a metai layer that possesses significantly

lower sheet resistance. The layout of transistor M! and MT is illustrated inFig. 2.7. They

were split into two separate banks of devices, with poly gate contacted at both ends.

Fig. 2.7: Transistor layout

2.7.2 Capacitor layout

The capacitoa are implemented as poly-poly structures with a dielectric oxide in

between. The capacitor structure has parasitic resistance associated with the resistance of

the polysilicon plates. This series resistance must be accounted for. If the capacitor is just a

bypass capacitor, the senes resistance may not rnatter, but if the capacitor is in the signal



path, the series resistance is critical, and cm significantly lirnit the performance of the

circuit.

In the circuit described in this work, three sets of signal coupling capacitors were used.

These capacitors rnust be laid out to reduce their senes resistance. This reduction can be

sirnply achieved by placing a large number of smdl capacitors in parallel, as shown in Fig.

2.8. with the overal l capacitance heine the desired coupling capacitor. This layout procedure

reduces the series resistance of the poly-poly capaciton by a factor equal to the number of

paralle1 capacitors used, thus reducing the resulting resistance [ I 11.

Via

One of small capacitors in parallel

Fig. 2.8: Capacitor layout

2.7.3 lnductor layout

Contact

' Metal and laye rs

The spiral inducton were assembled using ail three metal layers to minimize series

resistance. The typical layout of an inductor can be seen in Fig. 2.9. Sufficient space was

provided between inductors and their surroundings to keep unwanted parasitic effects from

affecting the inductors' electricai characteristics.



2.7.4 Final layout

The final layout of the LNA is illustrated in Fig. 2-10. The signal Row is from left to

right. The wiring for the signal paths in the layout must be wide enough to keep interconnect

resistance low so as to ensure the minimum signal loss. Also, metai Iayers are used as much

as possible for the same reason. Crossing between metal lines is kept to a minimum. The

physical layout in Fig. 2.10 corresponds to the electricai circuit topology shown in Fig. 2.6.

The area of the chip is 1.1x2.4 mm2 including bonding pads. Less than 5% of the chip area is

used for the active devices.



--

Fig. 2.1 O: Final full circuit layout

2.8 Post-Layout Simulation Results

The simulations of the design were done using Agilent's Advanced Design System

(ADS) md Spice models provided by Peregrine Semiconductor Corporation. The mode1 of

the inductors is a series LR from ports 1 to 2 with a parallel shunt capacitor C. These

inductor models c m be obtained using extracted equations provided by Peregrine [12].

Fig. 2.1 1 : Final circuit schematic for the LNA



The final circuit, dong with al1 bondwire inductors, is shown in Fig. 2.11. Al1 the

inductor values as well as parasitic resistance and capacitance are shown on the diagram.

S-parameters versus frequency are shown in Fig. 2.12. The power gain (SZ1) is very Rat

over the full band ( 1.93- 1.99GHz). The input and output reflection coefficient (S I I and S2*)

curves indicate good input and output matching and the reverse isolation (SI,) is better than

4SdB ovet the fuII band,

Fig. 2.12: S-parameters versus frequency for the LNA

- - -

A 1-V, CMOS on SOI. 1 -9-GHz CDMA Low Noise Amplifier University of Toronto


Intermodulation

Fig. 2.13 illustrates the LNA output spectrum when a two-tone RF input at

fl=1.960GHz and f2=1.965GHz is applied. The W output power level is Pfl=-34.465dBm

for each tone. The third-order intercept point referred to the output (OIP3) c m be calculated

using

where Pzfldfl is output power level at (2fl-f2)= i .955GHz. So, the output referred third-order

intercept (OIP3) is 19.25dBm. IIP3 is given by

IIP3 = OIP3 - (Power gain of the LNA)

and in this case is 3.6dBm.

! r c q . GHz

Fig. 2.13: LNA output spectrum using a two-tone RF input



The stability of the LNA was determined using Rollen's stability factor k which is

defined in terms of the S-panmeters of the amplifier by the equation [13]

w here

It wûs found that k is greater than one over the full band, implying that the LNA is

unconditionally stable.

The yield simulation of the design were also done using the ADS software within the

- 12db was 78% when al1 the passive full band. The yield for S21min=14dB, SI Imax=S22maK-- component values varied by t 10%. bondwire inductors varied by S0%. Process toleration

(including the variation of the threshold voltage) were taken into account.

Temperature effects

The temperature of the environment will definitely affect the performance of the LNA.

Table 2.1 gives the simulation results of the LNA at -50°C, 25°C and 75°C respectively.

Temperature has little impact on the characteristics of the LNA.



Table 2.1 : Simulation results of LNA at different temperatures - - - r Temperature 1 -500~ 1 25°C 1 7 5 0 ~

I ~ o w e r supply 1 IV 1 1 Frequency 1 1.96GHz 1 1.96GHz 1 1.96GHz 1 Noise figure 1 12.5dB* 1 9.5dB* 1 c2.5dB* y--.--- - - I 1 Gain 1 16.0dB / 15.8dB / 15.4dB

1 Power consumption 1 10.6mW 1 10.6rnW 1 10.9mW - - -

I n p u t return l o s ~ ISI1I 1 18.0dB 1 18.3dB 1 19.0dB 1 Output return loss IS221 1 18.6dB ( 18.6dB 1 l8.4dB

*First order analytical calculation

2.9 Summary

In this chapter, the power-constrained noise optimization of the input MOSFET and

design principles of the LNA were descnbed. Sources of noise in the LNA, the architecture,

design and layout of the amplifier as well as simulation results were presented. These

results meet the specifications for application in a CDMA transceiver operating in the 1.93-

1.99GHz band.



References H. T. Fnis, "Noise Figure of Radio Receivers", Proc. IRE, vol. 32, pp. 419-422, 1944.

T. H. Lee, The Design of CMOS Radio-freqitency Integrated Circuits, Cambridge Uni- versity Press, Cambridge, New York, NY, USA. 1998.

D. K. Shaeffer, The Design and implementation of low-power CMOS radio receivers, Kluwer Academic. Boston. USA, 1999.

A. van der Ziel, "Thermal Noise in Field EfFect Transistors," Proc. IEEE, pp. 1801- 1813, 1962.

A. A. Abidi, "High-frequency Noise Measurements on Fm's with Srnail dimensions," IEEE Trans. Electron Devices, vol. ED-33, pp. 180 1 - 1805, 1986. A. van der Ziel. Noise in Solid State Devices and Circuits, Wiley, New York, USA, 1986.

R. P. Jindal, "Noise Associated with Distributed Resistance of MOSFET Gate Struc- tures in Integnted Circuits," IEEE Trans. Electron Devices, vol. ED-3 1, pp. 1505- 1509, 1984.

B. Razavi, R.-H. Yan, and K. F. Lee, "Impact of Distributed Gate Resistance on the Performance of MOS Devices," IEEE Tram Circuits Syst. I , vol. 4 1, pp. 750-754, 1994.

N. G. Einspruch Ed., VLSI Electronics: Microstrrïcture Science, vol. 18, chapter 1, pp. 1-37, Academic Press, New York, 1989.

[IO] D. Shaeffer and T. H. Lee, "A [SV, 1.5GHz CMOS Low Noise Amplifier," IEEE J. Solid-State Circuits, vol. 32, pp.745-759, 1997.

[ I l ] R. S. Narayanaswami, The Design of A 1.9GHz Born W CMOS Power Amplifier For DECT, M.S. Thesis, University of California at Berkeley, 1996.

[12] Ultra Thin Silicon (UTSi) Lqoiit Rides and Design Manual, Peregrine Semiconductor Corporation, 1998.

[ 1 31 B. Razavi, RF Microelectronics, Prentice-Hall, NJ, 1998.

- - - - - - - -

A 1-V. CMOS on SOI, 1 .%GHz CDMA Low Noise Amplifier University of Toronto

Chapter 3: Experimental Results 37

CHAPTER 3

Experimental Results

3.1 The LNA Implementation

The micrograph of the LNA implemented using the 0.5ym double poly SOI CMOS

process provided by Peregrine Semiconductor Corporation is shown in Fig. 3.1 and

corresponds to the electrical circuit topology shown in Fig. 2.6. The chip was packaged in a

24-led cerarnic Hat package (24-Pin CFP). This package is suitable for frequencies up to

2GHz.

Fig. 3.2: Micrograph of the LNA

A 1-V, CMOS on SOI, f .%GHz CDMA Low Noise Amplifier University of Toronto

Chapter 3: Experimentai Results 38

The packaged LNAs were evaluated and tested using the Canadian Microelectronics

Corporation's PCB-TF2 printed circuit board test fixture [ I l . Typicai results obtained on a

sample of six chips are presented in the following sections.

3.2.1 Gain and noise figure

By ensuring appropriate DC bias and supply voltages, the gain and nois figure of the

LNA were tested. The gain test senip is shown in Fig. 3.2. The noise test setup is shown in

Fig. 3.3. The measured power gain and noise figure versus frequency (from 1.92 to 2.0GHz)

are shown in Fig. 3.4.

Fig. 3.2: Test setup for gain measurements

Noise Figure Noise Source Meter

Drive

HP346A

Noise )

source

Fig. 3.3: Test setup for noise figure measurements

A 1 -V, CMOS on SOI, 1 %GHz CDMA Low Noise Amplifier University of Toronto


- _ Simulation Gain - 0 -

' - 0 - - - 0 - - . ~ . . - O - O - . -

' O . - Measured Gain

frequency (GHz)

Fig. 3.4: Gain and noise figure versus frequency for the LNA

3.2.2 Reflection coefficient and reverse isolation

The input and output reflection coefficients (SI and S77) -- and the reverse isolation (S 12) were tested using a HP8720B network anaiyzer. The setup is shown in Fig. 3.5. Fig. 3.6

shows the measured input and output reflection coefficients (SI 1 and S 7 7 ) _- indicating good input and output matching. Fig. 3.7 shows the reverse isolation (S 12) which is better than

38.44dB over the full band.

t =P net aramets en+ Port 2

O Analyzer 1 Port 1 ' I G J L U G L

HP87206

Fig. 3.5: Test setup for S-parameter measurements

A I-V, CMOS on SOI, 1.9-GHz CDMA Low Noise Amplifier University of Toronto


-1 OdB -20dB -3068 -40dB

OdB -1OdB -20dB -30dB -40dB

Fig. 3.6: (a) Input and (b) output reflection coefficients for the LNA

Fig. 3.7: Reverse isolation (SI2) for the LNA

A f -V. CMOS on SOI, 1 -9-GHz CDMA Low Noise Amplifier uni ver si^ of Toronto

Chapter 3: Experirnental Results 41

3.2.3 Intermodulation distortion

The test setup for two-tone third-order intermodulation distortion measurements is

shown in Fig. 3.8. Generator frequencies (two-tones) were set at 1.950MHz and 1.955MHz

respectively. The tone levels were set so as not to saturate the LNA. The final output

spectrum of the LNA obtained from the spectrum andyzer is illustrated in Fig. 3.9. The

input refened third-order intercep (I[P?) was calculated to he 3dBm using the method

described in Chapter 2.

RF Generator Colby SG8000A

f1 T-connecter Power > -0 HP8563E , Combiner + LNA Spectrum Analyzer

RF Generator

Rohde & Schwarz Signal Generator ÇMT03

Fig. 3.8: Test setup for two-tone third-order intermodulation measurements

Fig. 3.9: Measured LNA output spectrum, two-tones power level -1 OdBm, third- order intermodulation power level -60.83dBm



3.2.4 Performance characteristics

Table 3.1 summarizes the characteristics of the LNA. Generaily, there is good

agreement between experimental and simulation characteristics.

Table 3.1 : Summary of LNA characteristics (25°C)

Power supply

1 Frequency 1 1.96GHz

Simulation

2.64mm2

I

1 Noise figure 1 1.9dB

Die area

1 Gain 1 14dB

Experimental

2.64mm2

1 Power consumption 1 1 0.6mW 1 f0.6mW 1 Input return Ioss IS1 1 1 17.4dB 1 18.3dB 1 1 Output return loss IS221 1 28.3dB 1 18.6dB 1 ( Reverse isolation ISI21 1 44.7dB 1 45.8dB 1 1 Terminal impedances 1 50Q I 5022 I

* First order analytical calculation

This chapter discussed the implementation and the experimental results of the LNA

implemented using 0Spm double poly SOI CMOS process provided by Peregrine

Semiconductor Corporation. The test results of the LNA were presented and are generally

in good agreement with simulations and expected specifications.

As outlined in Table 3.2, compared to previously reported SOI CMOS LNA designs,

the present design offers lower noise, high gain, low intermodulation distortion and on-chip

- - - - - - - - - -

A 1-V, CMOS on SOI, 1 -9-GHz CDMA Law Noise Amplifier University of Toronto


50R input output impedance matching. The LNA is viable for CDMA receiver application

in the I .93- 1.99GHz band.

Table 3.2: Measured performance and comparison with previous design

1 Main author, 1 This year [Ref.] , design

I

Johnson 1 Komumsaki. 1998 [2]

I 1998

Jin, 1 Harada, 1999 141 2000 [5!

I

1 Application 1 CDMA NIA 1 NIA PCS 1 N/A 0.5pm

Technology SOI 0.5pm 0.25pm SOI

0.61m 0.2prn SOI

1 Architecture ( L-Degen

1 Gain (dB) 1 14

-7.5 1 NIA 1 NIA -12 1 NIA NIA


Chapter 3: Experimentd Results 44

References Przhted Circuit Board Test F i ~ r e for 24-Pin CFP (PCF-TF2): User Guide, Canadian Microelectronics Corporation, Version 2.0, 1999.

R.A. Johnson, PR. Houssaye, C.E. Chang, P. Chen, M.E. Wood, G.A. Garcia, 1. Lagnado and P.M. Asbeck, "Advanced Thin-Film Silicon-on-Sapphire Technology: Microwave Circuit Applications ," IEEE Transactions on Electron Devices. vol. 45, pp. 1047- 1054, 1998.

H. Komurasaki, H. Sato, N. Sasaki, K. Ueda, S. Maeda, Y. Yamaguchi and T. Miki, "A Sub 1-V SOI CMOS Low Noise Amplifier for L-Band Applications," IEEE RF Inte- grated Circii ifs Symposium, Digest of Technical Papers, pp. 153- 1 56, 1998.

W. Jin, P.C.H. Chan and C. Hai, "1.5-V 1.8-GHz SOI Low Noise Amplifien for PCS Receivers," IEEE Int. SOI Conference, Proceedings, pp. 16- 17, 1999.

M. Harada, T. Tsukahara and J. Yamada, "0.5- 1 V 2 G b RF Front-end Circuits in CMOSISIMOX," ISSCC, Technical Digest, pp.378-379.2000.

- - - - - - - - - - - -


Chapter 4: Conclusions 45

Conclusions

This *ork dedt with the design of 3 !ow noise amplifier (LN.4) for the mdog front-end

of a wireless CDMA transceiver using CMOS on SOI technology. The use of this

technology may lead to an optimum single chip implementation of both the analog and

digital building blocks of a 1.9GHz transceiver operating from a IV supply. Such an

implementation offers reduced cost and improved reliability.

A Iow noise amplifier optimized for CDMA applications and operating in the 1.93-

1.99GHz band was designed and implemented using the 0.5pm double poly SOI CMOS

process provided by Peregrine Semiconductor Corporation. The inductive degeneration

topolopy used in the LNA implementation provides low noise and low power dissipation.

The LNA consists of two stages with onchip inductors and capacitors.

The experimental results at 1.96GHz show that the LNA has a 1.9dB noise figure, a

i4dB gain and a 3dBm iIP3. The LNA dso exhibits 17.4dB input and 28.3dB output return

losses respectively in a 50R system without extemal matching networks. The circuit draws

1 O.6mW from a 1 V supply and the chip area is 1.1~2.4 mm2.

Future work should focus on the use of more advanced technologies such as 0.25pm or

0.18pm CMOS on SOI processes which would provide MOSFETs with a higher unity gain

cutoff frequency. A LNA realized using such technologies is expected to operate at

frequencies in the 2-5GHz range with low noise and low power dissipation. Negative

feedback could be added to the circuit, if the LNA is used in wideband applications. The

performance of the amplifier could be further improved if inducton with a higher quaiity

factor are available.

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a cmos soi, cdma low noise amplifier · 2020. 4. 8. · a 1-v, cmos on soi, 1.9-ghz cdma low noise...

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