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EE141EE141--Spring 2006Spring 2006Digital Integrated Digital Integrated CircuitsCircuits

Lecture 4Lecture 4CMOS Manufacturing ProcessCMOS Manufacturing ProcessDesign RulesDesign Rules

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Good News!Good News!

We are moving to 155 Donner LabFrom Thursday, Feb 2We will be able to accommodate everyone!

Lab 2 starts on Monday!No swapping labsWe are trying to add another section

Homework #1 is due on ThursdayHomework #2 to be posted tomorrow, due next Thursday

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Class MaterialClass MaterialLast lecture

Brief introduction to CMOS inverter operation

Today’s lectureCMOS manufacturing process (Ch. 2.1-2.2)Design rules (Ch. 2.3)

Reading (2.1-2.2, 3.3.1-3.3.2)

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The MOS TransistorThe MOS TransistorPolysilicon

Aluminum

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MOS Transistors MOS Transistors --Types and SymbolsTypes and Symbols

D

S

G

D

S

G

G

S

D D

S

G

NMOS Enhancement NMOS

PMOS

Depletion

Enhancement

B

NMOS withBulk Contact

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A Modern CMOS ProcessA Modern CMOS Process

p-well n-well

p+

p-epi

SiO2

AlCu

poly

n+

SiO2

p+

gate-oxide

Tungsten

TiSi2

DualDual--Well Well ShallowTrenchShallowTrench--Isolated CMOS ProcessIsolated CMOS Process

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Transistor LayoutTransistor Layout

p-well SiO2

poly

SiO2

n+

Cross-Sectional View

Layout View

poly

p-well

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The Manufacturing ProcessThe Manufacturing Process

http://bwrc.eecs.berkeley.edu/IcBook

For a complete walk-through of the process (64 steps), check theBook web-page

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oxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a single photolithographic cycle (from [Fullman]).

PhotoPhoto--Lithographic ProcessLithographic Process

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Patterning of SiOPatterning of SiO22

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and depositionof negative photoresist

(c) Stepper exposure

PhotoresistSiO2

UV-lightPatternedoptical mask

Exposed resist

SiO2

Si-substrate

Si-substrate

Si-substrate

SiO2

SiO2

(d) After development and etching of resist,chemical or plasma etch of SiO2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Hardened resist

Chemical or plasmaetch

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CMOS Process at a GlanceCMOS Process at a GlanceDefine active areasEtch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drainregions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers

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CMOS Process WalkCMOS Process Walk--ThroughThrough

p+

p-epi (a) Base material: p+ substrate with optional p-epi layer

p+

(c) After plasma etch of insulatingtrenches using the inverse of the active area mask

p+

p-epi SiO2

3SiN

4(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)

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CMOS Process WalkCMOS Process Walk--ThroughThroughSiO2

(d) After trench filling, CMPplanarization, and removal of sacrificial nitride

(e) After n-well and VTp adjust implants

n

(f) After p-well andVTn adjust implants

p

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CMOS Process WalkCMOS Process Walk--ThroughThrough

(g) After polysilicon depositionand etch

poly(silicon)

(h) After n+ source/drain andp+source/drain implants. These

p+n+

steps also dope the polysilicon.

(i) After deposition of SiO2insulator and contact hole etch.

SiO2

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CMOS Process WalkCMOS Process Walk--ThroughThrough

(j) After deposition and patterning of first Al layer.

Al

(k) After deposition of SiO 2insulator, etching of via’s,deposition and patterning ofsecond layer of Al.

AlSiO2

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Advanced MetallizationAdvanced Metallization

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Design RulesDesign Rules

Interface between designer and process engineerGuidelines for constructing process masksUnit dimension: Minimum line width

scalable design rules: lambda parameterabsolute dimensions (micron rules)

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Design RulesDesign Rules

Intra-layerWidths, spacing, area

Inter-layerEnclosures, distances, extensions, overlaps

Special rules (sub-0.25µm)Antenna rules, density rules, (area)

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CMOS Process LayersCMOS Process LayersLayer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

RedBlue

MagentaBlack

BlackBlack

Select (p+,n+) Green

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Layers in 0.25 Layers in 0.25 μμm CMOS processm CMOS process

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IntraIntra--Layer Design RulesLayer Design Rules

Metal2 4

3

10

90

Well

Active3

3

Polysilicon2

2

Different PotentialSame Potential

Metal1 3

32

Contactor Via

Select2

or6

2Hole

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Transistor LayoutTransistor Layout

1

2

5

3

Tran

sist

or

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ViasVias and Contactsand Contacts

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2

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Select LayerSelect Layer

1

3 3

2

2

2

WellSubstrate

Select3

5

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CMOS Inverter LayoutCMOS Inverter Layout

A A’

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A’

A A’

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Layout EditorLayout Editor

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Design Rule CheckerDesign Rule Checker

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Sticks DiagramSticks Diagram

1

3

In Out

VDD

GND

Stick diagram of inverter

• Dimensionless layout entities• Only topology is important

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Circuit Under DesignCircuit Under DesignVDD VDD

Vin Vout

M1

M2

M3

M4

Vout2

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CMOS InverterCMOS Inverter

Polysilicon

In Out

VDD

GND

PMOS 2λ

Metal 1

NMOS

OutIn

VDD

PMOS

NMOS

Contacts

N Well

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Two InvertersTwo Inverters

Connect in Metal

Share power and ground

Abut cells

VDD

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Next LectureNext Lecture

Operation and modeling of the MOS transistor