ensure model quality improve vp debugging unleash more value fileensure model quality improve vp...

Ensure Model Quality Improve VP Debugging

Unleash More Value

Eugene Zhang

JEDA TechnologiesESCUG, March 11, 2008

2ESL Verification Automation™ - © 2008 JEDA Technologies, Inc

Virtual platform factsProblems and challengesObjectivesMethodology proposal► IP/Models with built-in checker►Reusable at system level

Methodology benefitsA TLM2 exampleSummary

Agenda


Users spend ~70% time ► Debugging models, IP’s, adapters

► Communicating about bug owner between platform provider and IP providers

► Building in-house capabilities on top of a VP

Unknown quality of the IP and platform models

Stable platform comes too late

Virtual Platform Development Facts


Lack of quantifiable quality measurementNeed for high quality IP models for fast platform developmentNeed for debug support to quickly identify problems Lack of effective IP interface/connectivity debugging mechanismLack of accuracy and correctness definitions at TLM

Problems and Challenges


Quickly assemble platform to explore alternative scenariosPerformance validationIdentify communication bottlenecks before committing RTL architecture Reuse platform and IP models for RTL verificationEarly SW developing and testing

Objectives for Virtual Platforms

It’s critical to have high quality, bug free IP and platform modelsMore analysis and debugging automation!


IP/model level► Introduce quantifiable IP quality metric

►Build assertion checker&coverage with IP core

►Make checker reusable for RTL verification

Platform level ►Reuse IP level checker for platform debugging

►Provide mechanism to switch checker on/off

►Make checker reusable for system level RTL verification

MethodologyQuality Control from IP to platform


Methodology Flow Model Creation and Testing

IP/Model

model testing env

IP release model

IP/ModelIntelligent Test Gen checker

coverage

coverage

checker


Methodology Flow Reuse at system level - an example

SoC Interconnect IP

MEMinput display2Dgfx

DSP uPDMAITG

checker

coverage

ON

OFF


Ease debugging at platform level

Identify protocol and communication bugs faster

Provide stable VP for SW development earlier

Users gets quality metric for IP models

Unleash the value of virtual platforms

Methodology Benefits


System Architects►Can explore more architectures in less time,

instead of debugging the platform models

SW developers►Can develop and integrate SW faster, instead

of debugging the platform models

RTL designer►Can re-use a high quality IP and platform as

a reference

Unleash the Value


Unleash the Valuesimplistic view

time

VP develop and debug until mature

arch design

SW development

RTL design tapeout

SW/HW integration

too little, too late

VP develop and debug until mature

Time savings!


A basic model quality metric►Transaction/data coverage

►SystemC code coverage

► ( Assertion checker is not included )

Testing -> measure -> improve testing -> measure again

A TLM2 Example


The TLM2 ExampleLT Temporal Decoupling

Two initiators, two targets on a bus

initiator


Transaction Coverage HighlightReport for traffic_generatorInstance: m_lt_initiator_1m_traffic_genSummary:Coverage: 87.5

Item Coverage ========================traffic_g_command 100 traffic_g_address 100 traffic_g_data_ptr 100traffic_g_response_status 50

SummaryCoverage: 50At Least: 1

Bin hits at least============================TLM_OK_RESPONSE 0 1TLM_INCOMPLETE_RESPONSE 29 1


Code Coverage Highlight


TLM2 coverage paper download:

www.jedatechnologies.net

Complete coverage report on OSCI TLM2 examples and Doulos examples:► [email protected]

More Details


Discussed a quality control/debugging methodology from IP to platforms

Make virtual platform stable early to unleash more value

Showed a TLM2 Example to measure model quality

Still many outstanding questions to be addressed by SystemC community

Summary

IP release model IP/Model

coverage

checker

Questions ?

ensure model quality improve vp debugging unleash more value fileensure model quality improve vp...

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